Board Design Guided Journeys for Agilex™ 7, Agilex™ 5 and Agilex™ 3 Devices
Design Hubs provide a Step-by-Step Guided Journeys for standard development flows surfacing the key critical resources and documentation.
Get Started
Introduction
Tools and Models
- IBIS Models for FPGA Devices
- SPICE Models for FPGAs
- EDA Tool Support Resource Center
- FPGA Development kits provide a variety of connector interfaces for transceivers
- Visit the Board Developer Center to view all the tools and models for your FPGA designs.
Guidelines and Documentation
Board Design - General Guidelines
Board Design - External Memory Interfaces Guidelines
Board Design - Transceivers Guidelines
- Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
- Agilex™ 5 FPGAs and SoCs PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN)
- AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing
- AN 529: Via Optimization Techniques for High-Speed Channel Designs
- AN 530: Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs
- AN 596: Modeling and Design Considerations for 10 Gbps Connectors
- AN 651: PCB Breakout Routing for High-Density Serial Channel Designs Beyond 10 Gbps
- AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
- AN 678: High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix® V Transceivers
- AN 684: Design Guidelines for 100 Gbps - CFP2 Interface
- AN 689: High Speed Channel Design Using the SFF-8431 Protocol
- AN 766: Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Additional Videos
Title |
Description |
|---|---|
Use the IBIS-AMI Model to Estimate Signal Integrity of Arria® 10 Transceiver |
Learn how to perform a signal integrity simulation with an Arria® 10 transceiver IBIS-AMI model in the Advanced Link Analyzer. Additionally, this video covers eye diagram reporting. |
Power Integrity
Power Management Resource Center
Altera develops FPGAs, SoCs and CPLDs using advanced process technologies that provide fast performance and high-logic density. The Power Management Resource Center helps you:
- Understand power consumption considerations when planning system designs.
- Estimate power requirements throughout the entire design flow.
- Manage and deliver power requirements using solutions from leading power-IC companies.
Power Analysis & Estimation Tools
| Early Power Estimators (EPE) and Power Analyzer | PowerPlay Power Analyzer Support Resources | Power Distribution Network |
|---|---|---|
| Estimate power consumption from concept through implementation. | Get help using the Power Analyzer Tool. | Design Tool used with FPGAs to optimize the board-level PDN. |
Power Resources
| FPGA Total Power Components Introduction | Power Supply Regulation | Power Supply Integrity | Thermal Management |
|---|---|---|---|
| Learn about FPGA power usage. | Learn how to choose a regulated voltage supply. | Describes proper bypassing and decoupling techniques. | Learn about power consumption and thermal management. |
Explore Other Developer Centers
For other design guidelines, visit the following Developer Centers:
Board Developer Center
Contains detailed guidelines and considerations for high-speed PCB designs with Altera® FPGAs and SoC FPGAs.
Embedded Software Developer Center
Contains guidance on how to design in an embedded environment with SoC FPGAs.
