Intel® Quartus® Prime Software Suite

The Intuitive High-Performance Design Environment.

Overview

The revolutionary Intel® Quartus® Prime Design Software includes everything you need to design for Intel® FPGAs, SoCs, and complex programmable logic device (CPLD) from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements are providing designers with the ideal platform to meet next-generation design opportunities.

More details are available in the Quick-Start for Intel® Quartus® Prime Pro Edition Software and the Getting Started User Guide: Intel® Quartus® Prime Pro Edition.

Features and Downloads

To compare different Intel® Quartus® Prime Editions, please visit the getting started page.

Intel® Quartus® Prime Pro Edition

The Intel® Quartus® Prime Pro Edition Software is optimized to support the advanced features in next-generation FPGAs and SoCs with the Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX device families.

Download now (paid license required)

Intel® Quartus® Prime Standard Edition

The Intel® Quartus® Prime Standard Edition Software includes extensive support for earlier device families in addition to the Intel® Cyclone® 10 LP device family.

Download now (paid license required)

Intel® Quartus® Prime Lite Edition

The Intel® Quartus® Prime Lite Edition software provides an ideal entry point to high-volume device families and is available as a free download with no license file required.

Download now (free, no license required)

What’s New in 21.1

Intel® Quartus® Prime Pro Edition Software v21.1 supports the newest FPGA family:

Intel® Agilex™ FPGAs

The Intel® Agilex™ FPGA family leverages heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm SuperFin Technology and 2nd Generation Intel® Hyperflex™ FPGA Architecture to deliver up to 45% higher performance (geomean vs. Intel® Stratix® 10)1 or up to 40% lower power1 for applications in Data Center, Networking, and Edge compute. Intel® Agilex™ SoC FPGAs also integrate the quad-core Arm Cortex-A53 processor to provide high system integration.

The Intel® Quartus® Prime Pro Edition Software v21.1 is an intuitive design environment that will help you meet your power and performance requirements and reduce your overall development effort. Features in the v21.1 release include:

  • Improvements for Intel® Agilex™ FPGA power, performance, runtime, memory, and logic utilization
  • New and improved Design Assistant design rules for synthesis, clock domain crossing (CDC), reset domain crossing (RDC), and timing
  • Hierarchical grouping of design rule checking (DRC)
  • Rule-tagging and filtering
  • DRC waiver mechanism
  • New ease-of-use reports for static timing analysis, design closure, synthesis, and undefined entities
  • More cross-probing and runtime improvements for reports
  • Locate SDC constraints in a file
  • Faster ECO compiles for post-fit tap targets in Signal Tap II Logic Analyzer
  • Flow-Resume feature
  • Improved GUI display for higher resolution monitors
  • Remote debug over Ethernet and PCI Express using Nios® II processor
  • Mark signals for debug (Beta) feature for register transfer level (RTL) development
  • Questa*-Intel® FPGA Edition Software (Beta Evaluation)
  • Updates to IP including
  • PCI Express
  • Interlaken
  • JESD
  • Transceivers
  • CPRI
  • ORAN
  • Ethernet

Introduction to Design Assistant

Get an overview of the new Design Assistant tool in the Intel® Quartus® Prime Pro Edition Software.

Timing Closure with Design Assistant

Design Assistant timing closure rules will help you find timing violations and get to closure faster.

Get More Out of Design Assistant

Learn how to filter and customize Design Assistant rules to fit your needs.

Using Virtual Pins

Virtual pins allow you to get resource estimates on partial designs with more I/Os than on the device.

Back Annotation Introduction

Preserve large block placement from one compilation to use as a starting point for future compilations.

Free Hands-On Training

Register for FREE instructor-led classes for hands-on training to enhance your FPGA design skills.

  • The Intel® Quartus® Prime Software: Foundation
  • Using Intel® Stratix® 10 and Intel® Agilex™ SoC FPGAs
  • Introduction to the Platform Designer System Integration Tool
  • The Quartus Software Debug Tools
  • Timing Closure with Intel® Quartus® Prime Pro Software
  • Intel® Quartus® Prime Pro Software Timing Analysis
  • Using Intel® SoC FPGAs
  • Introduction to Verilog HDL
  • Advanced Verilog HDL Design Techniques
  • And more!

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software.

Subscribe to the Intel® FPGA Newsletter

Do you want the latest info about Intel® FPGAs, Programmable Accelerators, and power solutions? Looking for hot tips on training and tools? Click here to subscribe to the Intel Inside Edge Monthly Newsletter.

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Mediante el envío de este formulario, usted confirma que es un adulto mayor de 18 años y acepta compartir su información personal con Intel para utilizarla con el propósito de satisfacer esta solicitud empresarial. También acepta suscribirse para permanecer al día sobre las últimas tecnologías de Intel y tendencias de la industria a través de correo electrónico y teléfono. Puede cancelar su suscripción en cualquier momento. Los sitios web y las comunicaciones de Intel están sujetos a nuestro Aviso de privacidad y nuestros Términos de uso.

Información sobre productos y desempeño

1

El desempeño varía según el uso, la configuración y otros factores. Más información en www.Intel.la/PerformanceIndex​.

Los resultados de desempeño se basan en pruebas realizadas a las fechas indicadas en las configuraciones y es posible que no reflejen todas las actualizaciones que están a disposición del público. Consulte las copias de seguridad para conocer los detalles de la configuración. Ningún producto o componente puede ser absolutamente seguro.

Sus costos y resultados pueden variar.