Intel® High Level Synthesis Compiler


The Intel® HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel® FPGAs. This tool accelerates verification time over RTL by raising the abstraction level for FPGA hardware design. Models developed in C++ are typically verified orders of magnitude faster than RTL.

Intel® HLS Compiler is included in the Intel® Quartus® Prime Design Software installation.

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Intel® HLS Compiler Success Story

Horizon Robotics is partnering with Intel to develop embedded AI applications. Learn how Horizon Robotics is using the Intel® Arria® 10 FPGA and Intel® HLS Compiler to do real-time pixel level segmentation for 3D semantic modeling and localization.


The Intel® HLS Compiler for Intel® Quartus® Prime Design Software provides various capabilities to enable hardware programmers to use C++ for accelerating their FPGA development process.

  • Uses untimed ANSI C++ as the golden design source
  • Allows you to quickly explore multiple architectures through high-level directives
  • Simplifies tool usage by inferring design intent from high-level constraints
  • Supports verification of RTL by comparison with the original C++ source model
  • Generates reusable intellectual property (IP) for system integration using the Platform Designer (formerly Qsys)
  • Supports inference of streaming, memory mapped, or wire interfaces
  • Performs device-specific timing-driven schedule optimization and technology mapping for Intel® FPGAs
  • Supports a software compiler use model and industry standards including ac_int data types
  • Detailed reporting feature for a birds-eye view: High-level design HTML reports are automatically generated during the simulation stage lets users see bottlenecks in their design
  • Allows users to view and analyze: Area utilization, loop structure, memory usage, system data flow, clusters, and surrounding logic
  • Supports multiple flows to integrate IP in a system. Integrate HLS code through direct HLD instantiation, through Platform Designer, or onto an Intel® Programmable Acceleration Card (Intel® PAC)

What's New in 20.1

An Intuitive Design Environment

  • Improved utilization and padding to reduce local memory usage for depths which are not a power of two.
  • New tutorials show how to improve fMAX certain loop operations and to improve concurrency.

Performance Improvements

  • Improved reporting and pragmas for fine-tuned control over loop fusion to merge sequential loops at the same level to improve throughput and reduce area.
  • Enabled stall enable clusters pragma to reduce local memory usage by removing FIFO instantiations and latency between functions. Pipe API enables arrays of high speed connectors for on chip data movement.

Getting Started

Documentation and Support

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