Select the persona that your work most closely aligns with to view your recommended training curriculum:

  • Software Developer for Host Application

Software developers writing applications for different markets that run on a CPU.  Very little to no knowledge of hardware, but want to take advantage of FPGA as an accelerator.  Typically build host applications in high level languages like Python and Java, but may use C/C++ and leverage optimized libraries for functions that have already been tuned for the hardware.

  • Software Developer for Acceleration Using OpenCL

Software developers that are architecting software applications for heterogenous systems that run on a CPU host, but target specific functions to different hardware accelerators using a common programming language, such as OpenCL.  These programmers not only write application code, but also optimize the acceleration
functions for the different accelerators such as FPGAs.

  • Software Developer for Acceleration using C/C++

Lower level software developers that are comfortable coding in C or C++ and are much more familiar  with details of the hardware and memory management.  These programmers are typically tuning and optimizing compute intensive function libraries for specific hardware.

  • FPGA Designer

Traditional FPGA developers that code in HLD languages such as Verilog HDL and VHDL.  These  developers are comfortable with creating FPGAs using the Intel Quartus Prime software, closing timing on complicated hardware circuits and managing complicated I/O interfaces to the FPGA.   

Training material is broken up into various levels of depth. 100 level is focused on introduction and high level overviews.  200 level covers the first level of how to do something, but expects basic understandings that are covered in the 100 level courses.  300 level goes down to a much deeper technical or specific level of knowledge.  

Software Developer for Host Applications

This curriculum is designed for software developers writing applications for different vertical markets that run on a CPU.  Very little to no knowledge of hardware is required.  You likely want to take advantage of the FPGA as an accelerator.  You typically build host applications in high level languages like Python and Java, but are familiar with C/C++ and leverage optimized libraries for functions that have already been tuned for the hardware.

Level 100 Courses

These 100 level courses are high level courses providing an introductory overview of topics that host application developers are interested in.   

Level 200 Courses

These 200 level courses are more in-depth follow-on courses to the 100 level, providing topics host application developers are interested in.  

Level 300 Courses

These 300 level courses are more advanced and in depth follow-on courses to the 200 level, providing topics host application developers are interested in.

 

Coming soon!

Software Developer for Acceleration using OpenCL

This curriculum is designed for software developers that are architecting software applications for heterogenous systems that run on a CPU host, but also offload specific functions to hardware accelerators using a common programming language, such as OpenCL.  These programmers not only write application code, but also tune and optimize the acceleration functions for the different accelerator platforms such as FPGAs.

Level 100 Courses

These 100 level courses are high level courses providing introductory level overviews to topics OpenCL application developers would be interested in.

Level 200 Courses

These 200 level courses are more in-depth follow-on courses to the 100 level, providing topics OpenCL acceleration developers would be interested in.   

Course Name Type Duration Language
OpenCL™ on FPGAs for Parallel Software Programmers Instructor Led / Virtual Class 8 Hours English
Introduction to OpenCL™ for Intel® FPGAs Instructor Led / Virtual Class 8 Hours English
インテル® FPGA 向け OpenCL*: 入門編
Instructor Led 8 Hours Japanese
インテル® FPGA 向け OpenCL* : 最適化編 Instructor Led 8 Hours Japanese
Introduction to OpenCL™ on FPGAs for Parallel Programmers Online 51 mins English
Introduction to Parallel Computing with OpenCL™ on FPGAs Online 26 mins English
用OpenCL在FPGA上实现并行计算 (Chinese Version: Introduction to Parallel Computing with OpenCL™ on FPGAs) Online 28 mins Chinese
OpenCL™ を使用した並列コンピューティング 入門編 (Japanese Version of Introduction to Parallel Computing with OpenCL) Online 32 mins Japanese
Writing OpenCL™ Programs for Intel® FPGAs Online 54 mins English
Intel FPGA 上的OpenCL编程方法 (Chinese Version: Writing OpenCL™ Programs for Intel® FPGAs) Online 61 mins Chinese
インテル® FPGA 向け OpenCL™ 実行方法 (Japanese Version: Writing OpenCL™ Programs for Intel® FPGAs) Online 63 mins Japanese
Running OpenCL™ on Intel® FPGAs Online 47 mins English
在Intel FPGA上运行OpenCL (Chinese Version: Running OpenCL™ on Intel® FPGAs) Online 45 mins Chinese
インテル® FPGA 向け OpenCL™ 実行方法 (Japanese Version: Running OpenCL™ on Intel® FPGAs) Online 54 mins Japanese
OpenCL™ Development with the Acceleration Stack for Intel® Xeon® CPU with FPGA Online 26 mins English
基于Intel®至强处理器和FPGA的加速栈的OpenCL™开发 (Chinese Version: OpenCL™ Development with the Acceleration Stack) Online 30 mins Chinese
インテル® アクセラレーション・スタック (インテル® Xeon® CPU + FPGA 対応) を使用した OpenCL™ 開発 (Japan. OpenCL Acceleration Stack) Online 33 mins Japanese

Level 300 Courses

These 300 level courses are more advanced and in-depth follow-on courses to the 200 level, providing topics host OpenCL accleration developers would be interested in.

Software Developer for Acceleration Using C/C++

This curriculum is designed for people who are lower level software developers that are comfortable coding in C or C++ and are much more familiar with details of the hardware and memory management.  These programmers are typically tuning and optimizing compute intensive function libraries for specific hardware platforms.

Level 100 Courses

These 100 level courses are high level courses providing introductory level overviews to topics C/C++ acceleration library developers would be interested in.

Level 200 Courses

These 200 level courses are more in-depth follow-on courses to the 100 level, providing topics C/C++ acceleration library developers would be interested in.   

Level 300 Courses

These 300 level courses are more advanced and in-depth follow-on courses to the 200 level, providing topics C/C++ accleration library developers would be interested in.

Course Name Type Duration Language
High-Level Synthesis Advanced Optimization Techniques Instructor Led / Virtual Class
8 Hours English
HLS Coding Optimizations for Intel® Stratix® 10 Devices Online 17 mins English

FPGA Designers

Traditional FPGA developers code in languages such as Verilog HDL and VHDL.  These developers are comfortable with creating FPGAs using the Intel Quartus Prime software, closing timing on complicated hardware circuits and managing complicated I/O interfaces to the FPGA.

100 Level Courses

These courses cover the basics of programmable logic design including FPGA design using VHDL or Verilog HDL. Learn how to set up and use the Intel® Quartus® software to create and run basic FPGA designs. The following table lists the recommended order of courses to take. 

Course Name Type Duration Language
Read Me First! Online 52 Minutes English
入门指南! (Chinese Version of Read Me First! ) Online 38 Minutes Chinese
インテル FPGAサイト ご利用ガイド (Japanese Version of Read Me First) Online 47 Minutes Japanese
Become a FPGA Designer in 4 Hours Online 4 Hours English
Basics of Programmable Logic: History of Digital Logic Design Online 21 Minutes English
Basics of Programmable Logic: FPGA Architecture Online 34 Minutes English
可编程逻辑基础:数字逻辑设计的历史 (Chinese Version: Basics of Programmable Logic: History of Digital Logic Design) Online 24 Minutes Chinese
可编程逻辑基础:FPGA架构 (Chinese Version: Basics of Programmable Logic: FPGA Architecture) Online 33 Minutes Chinese
プログラマブル・ロジックの基礎: デジタル・ロジック・デザインの歴史 (Japanese Basics: History of Digital Logic Design) Online 32 Minutes Japanese
プログラマブル・ロジックの基礎: FPGA アーキテクチャ (Japanese Version: Basics of Programmable Logic: FPGA Architecture) Online 57 Minutes Japanese
How to Begin a Simple FPGA Design Online 19 Minutes English
如何开始一个简单的FPGA设计 (Chinese Version of How to Begin a Simple FPGA Design) Online 14 Minutes Chinese
はじめてのFPGA設計 (Japanese Version of How to Begin a Simple FPGA Design) Online 21 Minutes Japanese
Introduction to Verilog HDL Instructor-Led / Virtual Class 8 Hours English
Verilog HDL Basics Online 50 Minutes English
Verilog HDL基础 (Chinese Version of Verilog HDL Basics) Online 39 Minutes Chinese
Verilog HDL 基礎編 (Japanese Version of Verilog HDL Basics) Online 49 Minutes Japanese
Introduction to VHDL Instructor-Led / Virtual Class 8 Hours English
Getting Started with VHDL (Europe) Instructor-Led Only 16 Hours German
VHDL Basics Online 92 Minutes English
VHDL基础 (Chinese Version of VHDL Basics) Online 45 Minutes Chinese
VHDL 基礎編 (Japanese Version of VHDL Basics) Online 68 Minutes Japanese
The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training) Instructor-Led / Virtual Class 8 Hours English
The Intel® Quartus® Prime Software: Foundation for Xilinx* Vivado* Design Suite Users Instructor-Led / Virtual Class 8 Hours English
Intel Quartus Prime Software: Pro Edition Features for High-End Designs Instructor-Led / Virtual Class 8 Hours English
Quartus II パーフェクト・コース I (Foundations) Instructor-Led Only 8 Hours Japanese
The Quartus Prime Software: Foundation (Standard Edition) (Online Training) Online 8 Hours English
The Quartus Prime Software: Foundation (Pro Edition) (Online Training) Online 8 Hours English

Quartus Prime 软件: 基础 (Pro Edition) (在线培训) (Chinese: The Quartus Prime Software: Foundation)

Online 8 Hours Chinese
Using the Quartus Prime Software: An Introduction Online 81 Minutes English
使用Quartus Prime 软件工具: 简介 (Chinese Version of Using the Quartus Prime Software: An Introduction) Online 68 Minutes Chinese
Quartus II開発ソフトウェア 基礎編:スタート・ガイド (Japanese Version of Quartus II Foundation: Getting Started) Online 47 Minutes Japanese
Quartus IIパーフェクト・コース:I/O プランニング (Japanese Version of Quartus II Foundation: I/O Planning) Online 33 Minutes Japanese
Quartus IIパーフェクト・コース:コンパイル (Japanese Version of Quartus II Foundation: Compilation) Online 33 Minutes Japanese
Quartus IIパーフェクト・コース:デザイン入力 (Japanese Version of Quartus II Foundation: Design Entry) Online 35 Minutes Japanese
Quartus IIパーフェクト・コース:プログラミングとコンフィギュレーション (Japanese Quartus II Foundation: Programming/Configure) Online 13 Minutes Japanese
Quartus IIパーフェクト・コース:設定とアサインメント (Japanese Version Quartus II Foundation: Settings Assignments) Online 24 Minutes Japanese

Introduction to Configuring Intel® FPGAs

Online 22 Minutes English
配置Altera FPGA的介绍 (Chinese Version of Introduction to Configuring Altera FPGAs) Online 20 Minutes Chinese
Configuration Schemes for Intel® FPGAs Online 26 Minutes English
Altera FPGA器件的配置方案 (Chinese Version of Configuration Schemes for Altera FPGAs) Online 21 Minutes Chinese
Configuration Solutions for Altera FPGAs Online 48 Minutes English
Altera FPGA 配置解决方案 (Chinese Version of Configuration Solutions for Altera FPGAs) Online 55 Minutes Chinese
Configuration for Stratix® 10 Devices Online 18 Minutes English
Stratix® 10 器件配置 (Chinese Version of Configuration for Stratix® 10 Devices) Online
18 Minutes Chinese
Stratix 10 デバイスのコンフィグレーション機能 (Japanese Version of Configuration for Stratix® 10 Devices) Online 22 Minutes Japanese
Synplify Pro Tips and Tricks Online 43 Minutes English
Synplify Synthesis Techniques with the Quartus II Software Online 30 Minutes English

Level 200 Courses

These courses assume that you understand the materials covered in the 100 Level courses. They cover more advanced topics, such as functional simulation, timing analysis, power analysis, debug, and system design using the Platform Designer (formerly Qsys).

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

 

Recommended Courses

Course Name Type Duration Language
Advanced Verilog HDL Design Techniques Instructor-Led / Virtual Class 8 Hours English
Advanced VHDL Design Techniques Instructor-Led / Virtual Class 8 Hours English
The Intel® Quartus® Prime Software Design Series: Timing Analysis Instructor-Led / Virtual Class 8 Hours English
Quartus II パーフェクト・コース II : タイミング解析 (Timing Analysis) Instructor-Led Only 8 Hours Japanese
Timing Analyzer: Introduction to Timing Analysis Online 15 Minutes English
时序分析器: 时序分析导论 (Chinese Version of Timing Analyzer: Introduction to Timing Analysis) Online 18 Minutes Chinese
Timing Analyzer: Timing Analyzer GUI Online 31 Minutes English
时序分析器: 时序分析器的GUI介绍 (Chinese Version of Timing Analyzer: Timing Analyzer GUI) Online 32 Minutes Chinese
Timing Analyzer: Intel Quartus Prime Integration & Reporting Online 25 Minutes English
时序分析器: Intel® Quartus® Prime软件中的集成&报告 (Chinese Timing Analyzer: Intel® Quartus® Prime Int. & Report) Online 26 Minutes Chinese
Timing Analyzer: Required SDC Constraints
Online 34 Minutes English
时序分析仪: 必需的SDC约束 (Chinese Version of Timing Analyzer: Required SDC Constraints) Online 34 Minutes Chinese
TimeQuestタイミング・アナライザ Online 100 Minutes Japanese
The Quartus Software Debug Tools Instructor-Led Only 8 Hours English
The Quartus II Software: Timing, Optimization and Debug (Europe) Instructor-Led Only 16 Hours German
Quartus IIパーフェクト・コース II :デバッグと解析ツール (Debugging and analysis tools) Instructor-Led Only 8 Hours Japanese
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Intro & Early Power Estimator Online 55 Minutes English
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Power Analyzer Online 27 Minutes English
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Optimization Online 51 Minutes English
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: SmartVoltage ID Online 16 Minutes English
功耗分析和优化 (Chinese Version: Power Analysis and Optimization) Online 67 Minutes Chinese
SignalTap II Logic Analyzer: Introduction & Getting Started Online 36 Minutes English
SignalTap II Logic Analyzer: Basic Trigger Conditions & Configuration Online 28 Minutes English
SignalTap II Logic Analyzer: Triggering Options, Compilation, & Device Programming Online 28 Minutes English
SignalTap II Logic Analyzer: Data Acquisition & Additional Features Online 30 Minutes English
SignalTap IIロジック・アナライザ Online 87 Minutes Japanese
SignalTap II嵌入式逻辑分析器 (Chinese Version of SignalTap II Embedded Logic Analyzer) Online 54 Minutes Chinese
Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction Online 38 Minutes English
Debugging JTAG Chain Integrity Online 32 Minutes English

Introduction to Platform Designer

Instructor-Led / Virtual Class 8 Hours English
Introduction to Platform Designer Online 26 minutes English
Intel 平台设计工具Platform Designer简介 (Chinese Version of Introduction to Platform Designer) Online 29 Minutes Chinese
Qsys 基礎編 (Japanese Version of Introduction to Qsys) Online 30 Minutes Japanese
Creating a System Design with Platform Designer: Getting Started Online 28 Minutes English
Creating a System Design with Platform Designer: Finish the System Online 35 Minutes English
使用Platform Designer创建系统设计: 入门 (Chinese: Create System Design w/ Platform Designer: Getting Started) Online 29 Minutes Chinese
使用Platform Designer创建系统设计:完成系统 (Chinese Create System Design w Platform Designer: Finish the System) Online 36 Minutes Chinese
Qsysを使用したシステム・デザインの生成方法 (Japanese Version of Creating a System Design with Qsys) Online 40 Minutes Japanese
Platform Designer in the Intel Quartus Prime Pro Edition Software Online 54 Minutes English

Incremental Block-Based Compilation in the Quartus Prime Pro Software: Introduction

Online 23 Minutes English
Incremental Block-Based Compilation in the Quartus Prime Pro Software: Design Partitioning Online 40 Minutes English
Incremental Block-Based Compilation in the Quartus Prime Pro Software: Timing Closure & Tips Online 22 Minutes English
Design Block Reuse in the Intel Quartus Prime Pro Software Online 45 Minutes
English
インテル® Quartus® Prime パーフェクト・コース II : デザイン最適化 Instructor-Led Only 8 Hours Japanese
Introduction to Incremental Compilation in the Intel® Quartus® Prime Standard Edition Software Online 184 Minutes English
渐进式编译入门 (Chinese Version of Introduction to Incremental Compilation) Online 116 Minutes Chinese
Quartus IIインクリメンタル・コンパイル入門 (Japanese Version of Introduction to Incremental Compilation) Online 110 Minutes Japanese
Quartus IIインクリメンタル・コンパイルによるチームベースのデザイン・フロー (Japanese Version of Team-Based Incremental Compilation) Online 70 Minutes Japanese
Overview of Mentor Graphic's ModelSim* Software Online 1 Hour English
ModelSim概要 Online 1 Hour Japanese

Optional Specialized Courses

Course Name Type Duration Language
Migrating to the Quartus Prime Pro Edition Software Online 34 Minutes English

Quartus Prime 開発ソフトウェアへの移行方法 (Japanese Version: Migrating to the Quartus Prime Pro Edition Software)

Online 34 Minutes
Japanese
Using Spectra-Q Synthesis in the Quartus Prime Software Online 32 Minutes English

Quartus Prime 開発ソフトウェアの Spectra-Q エンジンを使用した合成方法 (Japanese Version: Using Spectra-Q Synthesis)

Online 34 Minutes Japanese
Incremental Optimization with the Quartus Prime Pro Edition Online 26 Minutes English
Quartus Prime プロエディション・ソフトウェアが提供するインクリメンタル最適化機能 (Japanese Version: Incremental Optimization) Online 25 Minutes Japanese
SystemVerilog with the Quartus II Software Online 38 Minutes English
SystemVerilog和Quartus II 软件 (Chinese Version of SystemVerilog with the Quartus II Software) Online 34 Minutes Chinese
Quartus II によるSystemVerilogのサポート Online 32 Minutes Japanese
Creating Reusable Design Blocks: Introduction to IP Reuse Online 25 Minutes English
再利用可能なデザイン・ブロックの生成方法:IP再利用についての概要 (Japanese Ver Creating Reusable Blocks: Introduction to IP Reuse) Online 26 Minutes Japanese
Creating Reusable Design Blocks: IP Design & Implementation Online 42 Minutes English
再利用可能なデザイン・ブロックの生成方法:IPデザインとその実装 (Japanese Ver Creating Reusable Blocks: IP Design & Implementation) Online 45 Minutes Japanese
Creating Reusable Design Blocks: IP Integration with the Quartus II Software Online 25 Minutes English
再利用可能なデザイン・ブロックの生成方法:Quartus IIソフトウェアを使用したIPの統合 (Japanese Creating Reusable Blocks: IP Integration) Online 25 Minutes
 
Japanese
Good High-Speed Design Practices Online 36 Minutes English

Level 300 Courses

These 300 level courses are more advanced and in-depth follow-on courses to the 200 level, providing topics in specialty areas that FPGA developers would be interested in.

Use the up and down triangles on the right hand side to expand or collapse each specialty area for respective available courses.

Advanced Hardware

Recommended Courses

If you are an experienced hardware engineer and would like to develop advanced FPGA design skills, these are the courses for you. 

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Course Name Type Duration Language
Advanced Timing Analysis with TimeQuest Instructor-Led / Virtual Class 8 Hours English
Constraining Source Synchronous Interfaces Online 41 Minutes English
约束源同步接口 (Chinese Version of Constraining Source Synchronous Interfaces) Online 39 Minutes Chinese
Constraining Double Data Rate Source Synchronous Interfaces Online 29 Minutes English
约束双倍数据速率源同步接口 (Chinese Version of Constraining Double Data Rate Source Synchronous Interfaces) Online 29 Minutes Chinese
ダブル・データ・レートのソース同期インタフェースに対する制約 (Japanese Version of Constraining DDR Source Synchronous Interfaces) Online 35 Minutes Japanese
Advanced Qsys System Integration Tool Methodologies Instructor-Led / Virtual Class 8 Hours English
Advanced System Design Using Platform Designer: Component & System Simulation Online 28 Minutes English
Advanced System Design Using Platform Designer: System Verification with System Console Online 26 Minutes English
Advanced System Design Using Platform Designer: System Optimization Online 46 Minutes English
Advanced System Design Using Qsys: Utilizing Hierarchy in Qsys Designs Online 22 Minutes English
System Console Online 29 Minutes English
系统控制台 (Chinese Version of System Console) Online 35 Minutes Chinese
Avalon® Verification Suite Online 24 Minutes English
Avalon验证套装 (Chinese Version of Avalon Verification Suite) Online 17 Minutes Chinese
Custom IP Development Using Avalon and AXI* Interfaces Online 113 Minutes English
Chinese Version: Custom IP Development Using Avalon and AXI Interfaces Online 97 Minutes Chinese
AvalonおよびAXIインタフェースを使用したカスタム・コンポーネント開発 (Japanese Version of Custom IP Development) Online 117 Minutes Japanese
Low-Density Parity-Check (LDPC) Codes Intel® FPGA IP for 5G Systems Online   English

Advanced Hardware

Optional Specialized Courses

Learn how to close timing on your design. The Intel® Stratix® 10 Hyperflex™ classes will teach you advanced performance-boosting techniques that are applicable to any FPGA design. Other courses will teach you how to get the most from partial reconfiguration, scripting, and Intel® MAX® 10 devices.

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Course Name Type Duration Language
Building Custom Platforms for Intel® FPGA SDK for OpenCL™: Port from Arria® 10 GX Reference Platform Online 15 Minutes English
Building Custom Platforms for Intel® FPGA SDK for OpenCL™: Modifying a Reference Platform Online 33 Minutes English
Building Custom Platforms for Intel® FPGA SDK for OpenCL™: BSP Basics Online 50 Minutes English
Thermal Management in Intel Stratix 10 Devices Online 32 Minutes English
Intel Stratix 10 器件的散热管理 (Chinese Version: Thermal Management in Intel Stratix 10 Devices) Online 32 Minutes Chinese
High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Introduction, Architecture Online 30 Minutes English
High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: HBMC Features Online 20 Minutes English
High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: Implementation Online 23 Minutes English
Timing Closure with the Quartus® II Software Instructor-Led / Virtual Class 8 Hours English
Design Evaluation for Timing Closure Online 55 Minutes English
设计评估实现时序逼近 (Chinese Version of Design Evaluation for Timing Closure) Online 41 Minutes Chinese
Creating High-Performance Designs in Intel® Stratix® 10 FPGAs Online 45 Minutes English
Creating High-Performance Designs in 20 nm Intel FPGAs Online 41 Minutes English
インテル® 20 nm FPGAデバイスで高性能を実現する設計手法 (Japanese Creating High-Performance Designs in 20 nm Intel FPGAs) Online 49 Minutes Japanese
Mitigating Single Event Upsets in Intel® Arria® 10 and Intel Cyclone® 10 GX Devices Online 23 Minutes English

Arria 10 デバイスにおける SEU (Single Event Upset) の緩和技法 (Japanese Ver: Mitigating SEU in Arria 10 Devices)

Online 25 Minutes Japanese
SEU Mitigation in Intel FPGA Devices: Hierarchy Tagging Online 14 Minutes English
SEU Mitigation in Intel® FPGA Devices: Fault Injection Online 14 Minutes English
Performance Optimization with Intel Stratix 10 FPGA Hyperflex Architecture Instructor-Led / Virtual Class 8 Hours English
Advanced Optimization with Intel Stratix 10 FPGA Hyperflex Architecture Instructor-Led / Virtual Class 8 Hours English
The Intel Hyperflex FPGA Optimization Workshop Instructor-Led / Virtual Class 8 Hours English
Stratix 10 Hyperflex Architecture Overview Online 26 Minutes English

Stratix 10 Hyperflex 结构介绍 (Chinese Version of Stratix 10 Hyperflex Architecture Overview)

Online 22 Minutes Chinese

Stratix 10 Hyperflex アーキテクチャの概要 (Japanese Version of Stratix® 10 Hyperflex Architecture Overview)

Online 26 Minutes Japanese
Intel Quartus Prime Software Hyper-Aware Design Flow Online 17 Minutes English

Quartus II超感知设计流程 (Chinese Version of Quartus II Hyper-Aware Design Flow)

Online 25 Minutes Chinese

インテル® Quartus® Prime 開発ソフトウェア Hyper-Aware デザインフロー (Japanese Hyper-Aware Design Flow)

Online 19 Minutes Japanese
Using Fast Forward Compile for the Intel Hyperflex Architecture Online 25 Minutes English
为Hyperflex使用快速前向编译 (Chinese Version of Using Fast Forward Compile for the Hyperflex Architecture Online 24 Minutes Chinese

インテル® HyperFlex™ アーキテクチャーにおける Fast Forward Compile ツールの使用方法  (Japanese Fast Forward Compile)

Online 28 Minutes Japanese
Introduction to Hyper-Retiming Online 15 Minutes English
Hyper-Retiming 介绍 (Chinese Version of Introduction to Hyper-Retiming) Online 17 Minutes Chinese
Hyper-Retiming 入門編 (Japanese Version of Introduction to Hyper-Retiming) Online 22 Minutes Japanese
Eliminating Barriers to Hyper-Retiming Online 33 Minutes English

消除Hyper-Retiming中的障碍  (Chinese Version of Eliminating Barriers to Hyper-Retiming)

Online 30 Minutes Chinese

Hyper-Retimingの障壁を削除する方法 (Japanese Version of Eliminating Barriers to Hyper-Retiming)

Online 42 Minutes Japanese
Introduction to Hyper-Pipelining Online 28 Minutes English

Hyper-Pipelining入門編 (Japanese Version of Introduction to Hyper-Pipelining)

Online 30 Minutes Japanese

Intel® Hyperflex™ FPGA Architecture Design: Analyzing Critical Chains

Online 37 Minutes English
Introduction to Hyper-Optimization Online 22 Minutes English
Hyper 优化简介 (Chinese Version of Introduction to Hyper-Optimization) Online 24 Minutes Chinese

Hyper-Optimization 入門編 (Japanese Version of Introduction to Hyper-Optimization)

Online 24 Minutes Japanese
Hyper-Optimization Techniques 1: Loop Analysis and Solutions Online 22 Minutes English
Hyper-Optimization Techniques 2: Pre-Computation Online 9 Minutes English
Hyper-Optimization Techniques 3: Shannon's Decomposition Online 22 Minutes English
Using Design Space Explorer Online 21 Minutes English
デザイン・スペース・エクスプローラ (DSE) の使用 (Japanese Version of Using Design Space Explorer) Online 36 Minutes Japanese
使用Quartus II 顾问和设计空间勘查器实现时序逼近 (Chinese Version of Timing Closure Using Quartus II Advisors) Online 38 Minutes Chinese
Timing Closure Using TimeQuest Custom Reporting Online 24 Minutes English
Best HDL Design Practices for Timing Closure Online 61 Minutes English
时序逼近最佳HDL设计实践 (Chinese Version of Best HDL Design Practices for Timing Closure) Online 51 Minutes Chinese
タイミング収束のためのベストプラクティス (Japanese Version of Best HDL Practices for Timing Closure) Online 51 Minutes Japanese
Using Intel Quartus Prime Pro Software: Chip Planner Online 29 Minutes English
インテル Quartus Prime開発ソフトウェア・プロエディション: Chip Plannerの使用方法 (Japanese Chip Planner Pro Edition) Online 36 Minutes Japanese
Partial Reconfiguration with Arria 10 FPGAs Instructor-Led / Virtual Class 8 Hours English
Partial Reconfiguration for Intel Arria 10 Devices: Introduction & Project Assignments Online 40 Minutes English
Partial Reconfiguration for Intel Arria 10 Devices: Design Guidelines & Host Requirements Online 29 Minutes English
Partial Reconfiguration for Intel Arria 10 Devices: PR IP Core & Project Flow Online 34 Minutes English
Partial Reconfiguration for Intel Arria 10 Devices: Output Files & Demonstration Online 17 Minutes English
Partial Reconfiguration with Stratix V FPGAs Online 54 Minutes English
部分重配置 (Chinese Version of Partial Reconfiguration with Stratix V FPGAs) Online 51 Minutes Chinese
Using the MAX® 10 User Flash Memory Online 26 Minutes English
Using the MAX 10 User Flash Memory with the Nios® II Processor Online 24 Minutes English
Introduction to Remote System Upgrade in MAX 10 Devices Online 31 Minutes English
MAX 10器件远程系统更新(RSU)介绍 (Chinese Version of Introduction to Remote System Upgrade in MAX 10 Devices) Online 25 Minutes Chinese

MAX 10 デバイスのリモート・システム・アップグレード機能 (Japanese Introduction to Remote System Upgrade in MAX 10 Devices)

Online 35 Minutes Japanese
Remote System Upgrade in MAX 10 Devices: Design Flow & Demonstration Online 26 Minutes English
Max10器件远程系统更新(RSU):设计流程和示例 (Chinese Ver Remote System Upgrade in MAX 10 Devices: Design Flow & Demo) Online 23 Minutes Chinese
MAX 10 デバイスのリモート・システム・アップグレード機能:デザイン・フロー & デモンストレーション (Japanese Remote System Upgrade: Design Flow) Online 29 Minutes Japanese
Introduction to Tcl Online 65 Minutes English
Tcl 脚本语言入门 (Chinese Version of Introduction to Tcl) Online 54 Minutes Chinese
Quartus II Software Tcl Scripting Online 49 Minutes English
Quartus II 软件 Tcl 脚本 (Chinese Version of Quartus II Software Tcl Scripting) Online 40 Minutes Chinese
Quartus II Tclスクリプトの基礎 前編 Online 14 Minutes Japanese
Command Line Scripting Online 30 Minutes English
Managing Metastability with the Quartus II Software Online 58 Minutes English
Introduction to Analog to Digital Conversion in Intel® MAX® 10 Devices Online 21 Minutes English
Integrating an Analog to Digital Converter in Intel® MAX® 10 Devices Online 24 Minutes English
Using the ADC Toolkit in Intel® MAX® 10 Devices Online 27 Minutes English

I/O Interfaces

Recommended Courses

Reconfigurable devices allow you to use a large number of different high-speed I/O interfaces. These courses can help you understand the I/O blocks on Intel® FPGA devices in order to create your own custom I/O interfaces.

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Course Name Type Duration Language
Fast & Easy I/O System Design with Interface Planner Online 39 Minutes English

用BluePrint进行快捷的I/O系统设计 (Chinese Version: Fast & Easy I/O System Design with BluePrint)

Online 42 Minutes Chinese

BluePrint プラットフォーム・デザイナによる迅速で容易な I/O システム・デザイン (Japanese Fast & Easy I/O System Design w/ BluePrint)

Online 41 Minutes
 
Japanese
SERDES Channel Simulation with IBIS-AMI Models Online 14 Minutes English
IBIS-AMI モデルを使用したSerDesチャネルのシミュレーション (Japanese Ver: SerDes Channel Simulation with IBIS-AMI Models) Online 17 Minutes Japanese
Intel® Stratix® 10 FPGA L- and H-Tile Transceiver Basics Online 56 Minutes English
Transceiver Toolkit for Intel® Stratix® 10 Devices Online 56 Minutes English
Intel Stratix 10 收发器基础 (Chinese Version of Intel Stratix 10 Transceiver Basics) Online 45 Minutes Chinese
インテル Stratix 10 FPGA トランシーバー 基礎編 (Japanese version of Stratix 10 Transceiver Basics) Online 62 Minutes Japanese
Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer Online 39 Minutes English
Transceiver Basics for 20nm and 28 nm Devices Online 54 Minutes English
トランシーバー・ベーシック (Japanese Version of Transceiver Basics) Online 44 Minutes Japanese
收发器基础 (Chinese Version of Transceiver Basics) Online 49 Minutes Chinese
Building Gigabit Interfaces in 28 nm Devices Instructor-Led Only 8 Hours English
Transceiver Toolkit for 28 nm Devices Online 39 Minutes English
收发器工具包(Chinese Version of Transceiver Toolkit) Online 28 Minutes Chinese
Advanced Signal Conditioning for Stratix IV and Stratix V Receivers Online 19 Minutes English
Building Interfaces with Arria® 10 High-Speed Transceivers Instructor-Led or Virtual Class 8 Hours English
Advanced Signal Conditioning for Arria 10 FPGA Transceivers Online 32 Minutes English
Transceiver Toolkit for Intel® Arria® 10 and Cyclone® GX Devices Online 26 Minutes English
Generation 10 Transceiver Clocking Online 28 Minutes English
Building a Generation 10 Transceiver PHY Layer Online 37 Minutes English

I/O Interfaces

Optional Specialized Courses

Reconfigurable devices allow you to use a large number of different high-speed I/O interfaces.  These courses help you implement an interface to an external memory device or implement an industry standard communication interface such as Ethernet or PCI Express*.

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Course Name Type Duration Language
高速 I/O インタフェース: アルテラ FPGA を使った、外部メモリとのインタフェース (EMIF) Instructor-Led Only 8 Hours Japanese
Using High Performance Memory Interfaces in Altera® 28 nm and 40 nm FPGAs Online 85 Minutes English
使用Altera FPGA中的高性能存储器接口 (Chinese Version: Using High Performance Memory Interfaces in 28 nm & 40 nm FPGAs) Online 100 Minutes Chinese
Introduction to Memory Interfaces IP in Intel® FPGA Devices Online 44 Minutes English
第10代器件内存接口IP介绍 (Part 1) (Chinese Ver Introduction to Memory Interfaces IP in Arria 10 Devices) Online 23 Minutes Chinese
Generation 10デバイスのメモリ・インタフェース 導入編 (Japanese Ver of Intro to Memory Interfaces in Arria 10) Online 37 Minutes Japanese
Introduction to Hybrid Memory Cubes with Altera FPGAs Online 21 Minutes English
Integrating Memory Interfaces IP in Intel® FPGA Devices Online 62 Minutes English
第10代器件集成的内存接口IP (Part 2) (Chinese Version Integrating Memory Interfaces IP in Arria 10 Devices) Online 41 Minutes Chinese
Generation 10デバイスにおけるメモリ・インタフェースIPの統合 (Japanese Ver Integrating Memory Interfaces in Arria 10 Devices) Online 49 Minutes Japanese
Implementing the Hybrid Memory Cube Controller IP in an Altera FPGA Online 32 Minutes English
Verifying Memory Interfaces IP in Intel® FPGA Devices Online 31 Minutes English
第10代器件内存接口IP验证 (Part 3) (Chinese Version Verifying Memory Interfaces IP in Arria 10 Devices) Online 22 Minutes Chinese
Generation 10デバイスにおけるメモリ・インタフェースIPの検証 (Japanese Ver of Verifying Mem Interfaces in Arria 10 Devices) Online 28 Minutes Japanese
On-Chip Debugging of Memory Interfaces IP in Intel® FPGA Devices Online 30 Minutes English
第10代器件内存接口IP的片内调试 (Part 4) (Chinese Ver On-Chip Debug of Memory Interfaces IP in Arria 10 Devices) Online 16 Minutes Chinese
Generation 10デバイスにおけるメモリ・インタフェースIPのオンチップ・デバッグ (Japanese Version On-Chip Debug Memory Interfaces Arria 10) Online 22 Minutes Japanese
Creating PCI Express Links Using FPGAs Instructor-Led Only 8 Hours English
Introduction to the Arria 10 Hard IP for PCI Express Online 31 Minutes English
Customizing Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX FPGA Hard IP for PCI Express* Online 27 Minutes English
Connecting to the Arria 10 Hard IP for PCI Express Online 32 Minutes English
Designing with Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX Hard IP for PCI Express* Online 31 Minutes English
Introduction to the 28 nm Hard IP for PCI Express Online 37 Minutes English
Customizing the 28 nm Hard IP for PCI Express Online 35 Minutes English
Connecting to the 28 nm Hard IP for PCI Express Online 30 Minutes English
Designing with the 28 nm Hard IP for PCI Express Online 17 Minutes English
Getting Started with Altera's 40 nm PCI Express Solutions Online 92 Minutes English
アルテラ・トランシーバ搭載デバイスで実現する PCI Express Online 107 Minutes Japanese
Introduction to the Triple-Speed Ethernet MegaCore Function Online 28 Minutes English
Implementing the Triple-Speed Ethernet MegaCore Function Online 24 Minutes English
Altera 10/100/1000 Mb以太网解决方案简介 (Chinese Version of Intro to10/100/1000 Mb Ethernet) Online 66 Minutes Chinese
Introduction to the 10Gb Ethernet PHY Intel® FPGA IP Cores
Online 35 Minutes English
Introduction to the Low Latency 10Gb Ethernet MAC IP Core Online 30 Minutes English
Using the 10Gb Ethernet Design Examples Online 19 Minutes English
Configuring the Intel® Stratix® 10 FPGA E-Tile Hard IP for Ethernet  Online 17 Minutes English

JESD204B MegaCore IP Overview

Online 27 Minutes English

DSP

Recommended Courses

Do you have a digital signal processing (DSP) design that you would like to implement in an Intel® FPGA? These courses will teach you how to use the tools that can help create that design faster and more efficiently.

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Course Name Type Duration Language
Designing with DSP Builder for Intel® FPGAs Instructor-Led / Virtual Class 8 Hours English
DSP Builder Advanced Blockset: Getting Started Online 32 Minutes English
DSP Builder Advanced Blockset: Using Primitives Online 20 Minutes English

DSP Builder Advanced Blockset: Interfaces and IP Libraries

Online 25 Minutes English
采用DSP Builder高级模块库进行设计:简介(Chinese Version of DSP Builder Advanced Blockset: An Overview) Online 38 Minutes Chinese
Variable-Precision DSP Blocks in Altera 20 nm FPGAs Online 10 Minutes English
High-Performance Floating-Point Processing with FPGAs Online 48 Minutes English

DSP

Optional Specialized Courses

Course Name Type Duration Language
Building Video Systems Online 25 Minutes English
使用Altera视频工作台构建视频系统 (Chinese Version of Building Video Systems) Online 77 Minutes Chinese
Introduction to Graphics Online 12 Minutes English

Embedded

Recommended Courses

These courses will teach you how to create FPGA designs using the Nios® II or ARM* processors that are available on Intel® FPGA devices. 

The following table lists the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Course Name Type Duration Language
Designing with the Nios II Processor Instructor-Led Only 8 Hours English
組込みシステム: Nios II & Qsys 基礎編 (Embedded Systems: Nios II & Qsys Fundamentals) Instructor-Led Only 8 Hours Japanese
Using the Nios II Processor: Hardware Development Online 27 Minutes English
Using the Nios II Processor: Software Development Online 10 Minutes English
Using the Nios II Processor: Custom Components and Instructions Online 11 Minutes English
使用Nios II 处理器 (Chinese Version of Using the Nios II Processor) Online 64 Minutes Chinese
Nios II & Qsys(システム統合ツール) 基礎編 (Nios II & Qsys (system integration tool) Fundamentals) Online 8 Hours Japanese
Developing Software for the Nios II Processor Instructor-Led Only 8 Hours English
The Nios® II Processor: Introduction to Developing Software Online 30 Minutes English
The Nios® II Processor: Booting Online 20 Minutes English
Nios II ソフトウェアに搭載されたツールとそのデザイン・フロー (Japanese Version of Nios II Software Tools and Design Flow) Online 28 Minutes Japanese
Nios II ソフトウェアに搭載されたツールとそのデザイン・フロー (Japanese Version of Nios II Software Tools and Design Flow) Online 24 Minutes Chinese
Nios II プロセッサソフトウェア開発: デザイン・ツール概要 (Nios II processor software development: design tools Overview) Online 31 Minutes Japanese
Nios II 处理器开发软件:设计流程(Chinese Version of Nios II Processor: Design Flow) Online 24 Minutes Chinese
Nios II Software Tools for Eclipse:導入編 Online 17 Minutes Japanese
The Nios® II Processor: Hardware Abstraction Layer Online 34 Minutes English
Nios II 处理器开发软件:HAL入门 (Chinese Version of Nios II Processor: HAL Primer) Online 16 Minutes
Chinese
Nios II 处理器开发软件:HAL入门 (Chinese Version of Nios II Processor: HAL Primer) Online 14 Minutes Japanese
Lauterbach Debug Tools Online 16 Minutes English

Intel® Stratix® 10 SoC FPGA Technical Overview

Online 30 Minutes English
Designing with an ARM*-based SoC
Instructor-Led / Virtual Class 8 Hours English
ARMベース SoCハードウエア開発 (SoC Hardware) Instructor-Led Only 8 Hours Japanese
Hardware Design Flow for an ARM-based SoC Online 40 Minutes English
基于ARM的芯片系统硬件设计流程(Chinese Version: Hardware Design Flow for an ARM-based SoC) Online 47 Minutes Chinese
ARMベースSoC向けハードウェア・デザイン・フロー (Japanese Version: Hardware Design Flow for an ARM-based SoC) Online 53 Minutes Japanese
SoC ハードウエア概要 パート1(Japanese Version of SoC Hardware Overview Part 1) Online 68 Minutes Japanese
SoC ハードウェア概要 パート2 (Japanese Version of SoC Hardware Overview Part 2) Online 44 Minutes Japanese
Initial Design Review for Arria® 10 SoC FPGA Designs Online 28 Minutes English

SoC Hardware Overview: the Microprocessor Unit

Online 34 Minutes English
SoC 硬件概述: 微处理器单元 (Chinese Version of SoC Hardware Overview: the Microprocessor Unit ) Online 35 Minutes
 
Chinese

SoC Hardware Overview: Interconnect and Memory

Online 33 Minutes English

SoC 硬件综述: 互连和存储  (Chinese Version of SoC Hardware Overview: Interconnect and Memory)

Online 27 Minutes Chinese
SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals Online 26 Minutes English

SoC 硬件综述:系统管理,调试,及通用外围设备 (Chinese Ver of SoC Hardware Overview: System Mngmt, Debug, GP Peripherals)

Online 28 Minutes
 
Chinese
SoC Hardware Overview: Flash Controllers and Interface Protocols Online 20 Minutes English
SoC 硬件概述: Flash 控制器和接口协议 (Chinese SoC Hardware Overview: Flash Controllers and Interface Protocols) Online 20 Minutes Chinese
Developing Software for an ARM-based SoC Instructor-Led / Virtual Class 8 Hours English
ARM ベース SoC ソフトウエア開発 Instructor-Led Only 8 hours
Japanese
Software Design Flow for an ARM-based SoC Online 27 Minutes English
基于ARM的SoC的软件设计流程(Chinese Version: Software Design Flow for an ARM-based SoC) Online 33 Minutes Chinese
ベース SoC 向けソフトウェア・デザイン・フロー (Japanese Verion of Software Design Flow for ARM-based SoC) Online 40 Minutes Japanese
Profiling Intel® SoC FPGAs with Arm* Streamline Online 26 Minutes English
Creating Second Stage Bootloader for Altera® SoCs Online 31 Minutes English
Getting Started with Linux* OS for Intel SoC FPGAs Online 37 Minutes English
アルテラ SoC 向け Linux の概要 (Japanese Version of Getting Started with Linux for Altera SoCs) Online 57 Minutes
Japanese
SoC Bare-metal Programming and Hardware Libraries Online 28 Minutes English
Secure Boot with Arria® 10 SoC FPGAs Online 17 Minutes English

University Coursework

Intel® FPGA offers full semester educational materials that include tutorials, laboratory exercises, intellectual property (IP) cores, computer systems examples, and software. They are used in university FPGA centric courses on digital logic, computer organization, embedded systems, and machine learning.  

Want to learn more?  Go to the Univeristy Pages.