ID:13034 The following nodes have both tri-state and non-tri-state drivers
CAUSE: The design contains some nodes or pins that should be driven by tri-state logic, but are driven by non-tri-state logic. As a result, the Quartus Prime software inserted always-enabled tri-state buffers to make the netlist valid.
For example, the following Verilog design gives this warning:
module test1 (input in1, in2, in3, oe1, oe2, output out1, inout bi1, inout bi2); reg tri_wire; wire tmp_bidir; always @ (*) begin if (oe1) tri_wire <= in1; else if (oe2) tri_wire <= in2; else tri_wire <= 1'bZ; end assign out1 = tri_wire; assign bi1 = tri_wire; nand (tmp_bidir, bi1, in3); assign bi2 = tmp_bidir; endmoduleIn the design test1, the bidir pin bi2 is driven by non-tri-state logic. As a result, this warning will be given for that pin. The following design also gives this warning for the output pin out.
module test2 (input in1, in2, in3, oe1, oe2, output out); reg tri_wire; wire tmp_bidir; assign out = oe1 ? in1 : 1'bz; assign out = oe2 ? in2 : 1'bz; assign out = in3; endmoduleSee the subsequent sub-messages for a list of the affected pins.
ACTION: See the sub-messages of this message.