Intel® FPGAs and Programmable Devices / SoCs / Portfolio / Arria V SoC / Arria® V SoC FPGAs Support

Arria® V SoC FPGAs Support

  • Arria® V I/O Timing Spreadsheet
  • Arria V SoC Device Design Guidelines 
  • Arria V FPGA Device Design Guidelines (PDF)
  • Arria V SX and ST SoC Errata
  • Arria V GX and GT Errata (PDF)
  • Arria V GZ Errata (PDF)
  • Arria V ES Errata and Guidelines (PDF)
  • Known Arria V Issues
  • Arria V SoC HPS Address Map and Register Definitions (HTML)
  • Arria V SoC HPS Address Map and Register Definitions (ZIP)
  • All Packaging Specifications and Dimensions
  • Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines (PDF)
  • Device Pin-Outs
  • BSDL Files
  • Board Design Guidelines
  • Arria V SoC HPS Supported Flash Devices

QUICK LINKS

  • Arria V Device Datasheet
  • Arria V SX and ST SoC Errata
  • Documentation: Pin-Out Files for Intel FPGA Devices

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Document PDF Published Date Filter Doc Type Filter Collections Filter
Advanced Link Analyzer User Guide 2020-12-16 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide
Embedded Peripherals IP User Guide 2020-12-23 altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property,altera:development-software
Intel FPGA Software Installation and Licensing 2020-12-14 altera:document-type/reference-manual,altera:document-type/user-guide altera:development-software
Nios II Processor Reference Guide 2020-10-22 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:development-software
10-Gbps Ethernet (10GbE) MAC IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
100G Interlaken IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes altera:intellectual-property
10GBASE-R PHY IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes altera:intellectual-property
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
50G Interlaken IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes altera:intellectual-property
ALTDQ_DQS2 IP Core User Guide 2017-05-08 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide
ALTERA_CORDIC IP Core User Guide 2017-05-08 altera:document-type/user-guide altera:intellectual-property
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller 2017-09-22 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/app-notes
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines 2015-05-04 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/app-notes
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ) 2016-05-20 altera:document-type/app-notes
AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) 2015-12-30 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/app-notes altera:intellectual-property
AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design 2015-12-14 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/app-notes altera:intellectual-property
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) 2015-11-02 altera:content-area/pcb-layout-and-packaging altera:document-type/app-notes
Altera 1588 System Solution 2016-01-28 altera:document-type/app-notes,altera:document-type/design-guides altera:intellectual-property
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide 2017-06-16 altera:content-area/clocking altera:document-type/user-guide altera:intellectual-property
Arria V Avalon-ST Interface for PCIe Solutions User Guide 2017-05-12 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
Arria V Hard IP for PCI Express IP Core Release Notes 2016-10-31 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
Arria V SX and ST SoC Errata 2015-07-14 altera:document-type/errata-sheets altera:collection/data-sheet,altera:content-area/recommended-documents
Configuring Altera FPGAs 2014-12-15 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide
Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide 2017-06-19 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
High-speed Reed-Solomon IP Core Release Notes 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/release-notes altera:intellectual-property
Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices 2013-12-06 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/app-notes
Intel Quartus Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization 2017-11-06 altera:document-type/user-guide altera:development-software
LDPC IP Core User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Nios II Embedded Design Suite Release Notes 2015-06-17 altera:document-type/release-notes,altera:document-type/design-guides
PCI Express Avalon -MM DMA Reference Design 2017-05-08 altera:document-type/app-notes
PowerPlay Early Power Estimator User Guide 2017-02-21 altera:content-area/power-and-thermal-management altera:document-type/user-guide altera:content-area/recommended-documents,altera:development-software
SDI Audio IP Cores Release Notes 2017-05-08 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
SerialLite II IP Core Release Notes 2017-05-08 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes altera:intellectual-property
Using the Altera PDN Tool to Optimize Your Power Delivery Network Design 2015-07-08 altera:content-area/power-and-thermal-management altera:document-type/app-notes
Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices 2015-12-04 altera:document-type/app-notes
Viterbi IP Core User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
ALTIOBUF IP Core User Guide 2020-01-13 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
AN 706: Routing HPS Peripheral Signals to the FPGA External Interface 2018-05-07 altera:document-type/app-notes altera:content-area/recommended-documents
AN 796: Cyclone V and Arria V SoC Device Design Guidelines 2020-07-27 altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/development-kits altera:document-type/app-notes altera:intellectual-property,altera:content-area/recommended-documents,altera:development-software
Arria V Avalon-MM Interface for PCIe Solutions User Guide 2017-05-21 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
Arria V Avalon-ST Interface for PCIe Solutions User Guide 2019-05-03 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
Arria V Device Datasheet 2019-04-26 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management altera:document-type/data-sheets altera:collection/data-sheet,altera:content-area/recommended-documents
Arria V Device Handbook: Volume 1: Device Interfaces and Integration 2020-07-24 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management altera:document-type/user-guide altera:content-area/recommended-documents
Arria V Hard Processor System Technical Reference Manual 2020-09-03 altera:content-area/hard-processor-system altera:document-type/reference-manual,altera:document-type/user-guide altera:content-area/recommended-documents
BCH Intel FPGA IP: User Guide 2018-11-30 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Battery Management System Reference Design 2016-04-02 altera:document-type/reference-manual altera:development-software
Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide 2020-09-04 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms 2016-12-13 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/embedded-memory---dsp altera:document-type/app-notes,altera:document-type/design-guides altera:development-software
Differences Among Intel SoC Device Families 2018-08-22 altera:content-area/external-memory-interface,altera:content-area/hard-processor-system altera:document-type/reference-manual,altera:document-type/user-guide altera:content-area/recommended-documents
Embedded Design Handbook 2020-07-22 altera:content-area/embedded-memory---dsp altera:document-type/design-guides,altera:document-type/user-guide altera:development-software
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide 2020-03-11 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
FFT IP Core: User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Guidelines for Developing a Nios II HAL Device Driver 2015-06-12 altera:document-type/app-notes,altera:document-type/design-guides
High-speed Reed-Solomon IP Core User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Intel FPGA Software Installation and Licensing Quick Start 2018-11-26 altera:document-type/user-guide altera:development-software
Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis 2018-05-09 altera:document-type/user-guide altera:development-software
Intel Quartus Prime Standard Edition Handbook Volume 3 Verification 2018-05-09 altera:document-type/user-guide altera:development-software
Intel SoC FPGA Embedded Development Suite (SoC EDS) Professional Version 20.1 Release Notes 2020-04-24 altera:content-area/hard-processor-system altera:document-type/release-notes altera:development-software
Intel SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 20.1 Release Notes 2020-06-12 altera:content-area/hard-processor-system altera:document-type/release-notes altera:development-software
Intel SoC FPGA Embedded Development Suite User Guide 2020-08-07 altera:content-area/hard-processor-system altera:document-type/user-guide
LVDS SERDES Transmitter / Receiver IP Cores User Guide 2017-12-15 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
NCO IP Core: User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Reed-Solomon II IP Core User Guide 2016-05-02 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Remote Update Intel FPGA IP Core Release Notes 2018-05-07 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/release-notes
SerialLite II IP Core User Guide 2019-01-09 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
Unique Chip ID Intel FPGA IP Core Release Notes 2018-05-07 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/release-notes
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide 2018-07-31 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
External Memory Interfaces
  • Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions (ver 1.0, Nov 2011, 589 KB)
Power and Thermal Management
  • Arria II and Arria V PowerPlay Early Power Estimator 
    (Final)
    PowerPlay Early Power Estimator User Guide
  • An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs 
    (BDTI)
  • AN 657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices 
  • Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
    Power Delivery Network (PDN) Tool 2.0 for Stratix® V, Arria V, Arria II GZ, Cyclone® V, and Cyclone IV Devices (5 MB)
    Power Delivery Network (PDN) Tool 2.0 for Arria 10 Devices (3 MB)
  • Meeting the Low Power Imperative at 28 nm
I/O Interfaces, Protocols and Signal Integrity
  • AN 456: PCI Express* High Performance Reference Design
  • AN 696: Using the JESD204B MegaCore Function in Arria V Devices
  • Altera JESD204B MegaCore Function and ADI AD9250 Hardware Checkout Report
    AN 696 Reference Design Example (3 MB)
  • Arria V Avalon®-MM Interface for PCIe* Solutions User Guide
  • Arria V Avalon-ST Interface for PCIe Solutions User Guide
  • Arria V Hard IP for PCI Express User Guide
  • AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs
  • AN 668: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices
    Arria V GX Design Files (2 MB)
    Stratix V GX Design Files (1 MB)
  • AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
  • AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
  • AN 653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core
    AN 653_Reference_Design_File (346 KB)
  • Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
  • Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
  • Early SSN Estimator User Guide for Altera Programmable Devices
    Arria V Early SSN Estimator (528 KB)
  • V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Embedded Memory
  • Real-Time Challenges and Opportunities in SoCs 
DSP
  • Intel FPGA Product Catalog 
  • Altera's 28 nm Device Portfolio
Device Configuration and Remote System Upgrades
  • Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
    user_led.zip (4 KB)
Design Guidelines
  • AN 652: Arria V Timing Optimization Guidelines
  • Achieving SerDes Interoperability on Altera's 28 nm FPGAs Using Introspect ESP (Introspect)
  • AN 662: Arria V and Cyclone V Design Guidelines
  • AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
    AN 676 Reference Design Example
  • An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs
  • Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP
  • Real-Time Challenges and Opportunities in SoCs
  • Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach
  • Tips and Techniques for 28 nm Design Optimization
PCB Layout and Packaging
  • AN 659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array
  • AN 657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices
Development Kits
  • Intel FPGA Product Catalog
  • Arria V GT FPGA Development Board Reference Manual
  • Arria V GT FPGA Development Kit User Guide
  • Arria V GX FPGA Development Board Reference Manual
  • Arria V GX FPGA Development Kit User Guide
  • Arria V GX Starter Board Reference Manual
  • Arria V GX Starter Kit User Guide
  • Arria V SoC Development Board Reference Manual
  • Arria V SoC Development Kit User Guide
End Applications
  • AN 717: Nios® II Gen2 Hardware Development Tutorial
  • A Validated Methodology for Designing Safe Industrial Systems on a Chip 
  • Altera and Escape Communications' Microwave Modem Solution 
  • Altera's 28 nm Device Portfolio 
  • AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
  • Broadcast Design Solutions from Altera 
  • Optimize Motor Control Designs with an Integrated FPGA Design Flow 
  • OTN Family | 200G P-OTS Any-Rate Mapper | TPOC226 (SoftSilicon function)
  • OTN Family | 400G Transponder / Muxponder | TPO516 (SoftSilicon function)
  • Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach
General Device Documentation
  • Differences Among Intel SoC Device Families
  • Altera QAM Design Solution for HD Video 
  • Intel User-Customizable SoC FPGAs 
  • Designing Polyphase DPD Solutions with 28-nm FPGAs 
  • FPGA-Adaptive Software Debug and Performance Analysis 
  • Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs 
  • Industrial Motor Drive on a Single FPGA 
  • Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP 
  • Optimize Power and Cost with Altera’s Diversified 28-nm Device Portfolio 
  • Robust Image Format Conversion Solutions

Related Links

  • SoC Overview
  • Architecture Matters
  • SoC Resource Guide