Intel Quartus Prime Pro Edition User Guide: Design Optimization
Design Optimization Overview
Optimization of a FPGA design requires a multi-dimensional approach that meets the design goals while reducing area, critical path delay, power consumption, and runtime. The Intel® Quartus® Prime software includes advisors to address each of these issues. By implementing the advisor's suggestions, you can reduce the time spent on design iterations.
Device Considerations
Device Migration Considerations
When choosing a design's target device in the Intel® Quartus® Prime software, you can see a list of compatible devices by clicking the Migration Devices button in the Device dialog box.
Required Settings for Initial Compilation
Guidelines for I/O Assignments
- When specifying I/O assignments, make sure that the Intel® Quartus® Prime software is using an accurate I/O timing delay for timing analysis and Fitter optimizations.
- If the PCB layout does not indicate pin locations, then leave the pin locations unconstrained. This technique allows the Compiler to search for the best layout. Otherwise, make pin assignments to constrain the compilation appropriately.
Guidelines for Time Constraints
For best results, use real time requirements. Applying more demanding timing requirements than the design needs can cause the Compiler to trade off by increasing resource usage, power utilization, or compilation time.
Comprehensive timing requirement settings achieve the best results for the following reasons:
- Correct timing assignments enable the software to work hardest to optimize the performance of the timing-critical parts of the design and make trade-offs for performance. This optimization can also save area or power utilization in non-critical parts of the design.
- If enabled, the Intel® Quartus® Prime software performs physical synthesis optimizations based on timing requirements.
The Intel® Quartus® Prime Timing Analyzer determines if the design implementation meets the timing requirement. The Compilation Report shows whether the design meets the timing requirements, while the timing analysis reporting commands provide detailed information about the timing paths.
Trade-Offs and Limitations
Trade-off | Comments |
---|---|
Resource usage and critical path timing. | Certain techniques (such as logic duplication) can improve timing performance at the cost of increased area. |
Power requirements can result in area and timing trade-offs. | For example, reducing the number of available high-speed tiles, or attempting to shorten high-power nets at the expense of critical path nets. |
System cost and time-to-market considerations can affect the choice of device. | For example, a device with a higher speed grade or more clock networks can facilitate timing closure at the expense of higher power consumption and system cost. |
Finally, constrains that are too severe limit design feasibility as far as no possible solution for the selected device. If the Fitter cannot resolve a design due to resource limitations, timing constraints, or power constraints, consider rewriting parts of the HDL code.
Reducing Area
Reducing Critical Path Delay
By default, the Intel® Quartus® Prime Fitter works to meet the timing requirements, and stops when the requirements are met. Therefore, realistic constraints are crucial for timing closure.
Under-constrained designs can lead to sub-optimal results. For over-constrained designs, the Fitter might over-optimize non-critical paths at the expense of true critical paths. In addition, area and compilation time may also increase.
For designs with high resource usage, the Intel® Quartus® Prime Fitter might have trouble finding a legal placement. In such circumstances, the Fitter automatically modifies settings to try to trade off performance for area.
The Intel® Quartus® Prime Fitter offers advanced options that can help improve the design performance when you properly set constraints. Use the Timing Optimization Advisor to determine which options are best suited for the design.
In high-density FPGAs, routing accounts for a major part of critical path timing. Because of this, duplicating or retiming logic can allow the Fitter to reduce delay on critical paths. The Intel® Quartus® Prime software offers push-button netlist optimizations and physical synthesis options that can improve design performance at the expense of considerable increases of compilation time and area. Turn on only those options that help you keep reasonable compilation times and resource usage. Alternately, you can modify the HDL to manually duplicate or adjust the timing logic.
Reducing Power Consumption
Reducing Runtime
The Intel® Quartus® Prime software supports parallel compilation in computers with multiple processors. This can reduce compilation times by up to 15%.
Intel Quartus Prime Software Tools for Design Optimization
Design Visualization Tools
The Intel® Quartus® Prime software provides tools that display graphical representations of a design.
Tool | Description |
---|---|
RTL Viewer | Provides a schematic representation of the design before synthesis and place-and-route. |
Technology Map Viewer | Provides a schematic representation of the design implementation in the selected device architecture after synthesis and place-and-route. Optionally, you can include timing information. |
Design Partition Planner | Displays designs at partition and entity levels, and can display connectivity between entities |
Design Partition Planner and Chip Planner | Allow you to partition and layout the design at a higher level. |
Chip Planner | Allow you to make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. |
Advisors
The advisors provide recommendations based on the project settings and design constraints. Those recommendations can help you to fit the project, meet timing or power requirements, or improve the design performance.
The advisors organize the recommendations from general to specific. Where applicable, the categories are divided into of stages presented by complexity.
- Timing Optimization Advisor
- Power Optimization Advisor
- Compilation Time Advisor
Design Exploration
Design Space Explorer II
If a design is close to meeting timing or area requirements, you can try different seeds with the DSE II, and find one seed that meets timing or area requirements.
You can run DSE II at any step in the design process; however, because large changes in a design can neutralize gains achieved from optimizing settings, Intel® FPGA recommends that you run DSE II late in the design cycle.
How DSE II Works
In DSE II, an exploration point is a collection of Analysis & Synthesis, Fitter, and placement settings, and a group of exploration points is a design exploration. A design exploration can also include different fitter seeds.
DSE II compiles the design using the settings corresponding to each exploration point. When the compilation finishes, DSE II evaluates the performance data against an optimization goal that you specify. You can direct the DSE II to optimize for timing, area, or power.
Use of Computing Resources
If you have a laptop or standard computer, you can use the single compilation feature to compile your design on a workstation with higher computing performance and memory capacity.
When running on a compute farm, you can direct the DSE II to safely exit after submitting all the jobs while the compilations continue to run until completion. Optionally, you can receive an e-mail when the compilations are complete.
If you launch jobs using SSH, the remote host must enable public and private key authentication. For private keys encrypted with a pass phrase, the remote host must run the ssh key agent to decrypt the private key, so the quartus_dse executable can access the key.
Optimization Parameters
DSE II provides a collection of predefined exploration spaces that focus on what you want to optimize. Additionally, you can define a set of compilation seeds. The number of explorations points is the number of seeds multiplied by the number of exploration modes.
In the DSE GUI, you specify these settings in the Exploration page.
Result Management
DSE II compares the compilation results to determine the best Intel® Quartus® Prime software settings for the design. The Report page displays a summary of results.
In an exploration, DSE II selects the best worst-case slack value from among all timing corners across all exploration points. If you want to optimize for worst-case setup slack or hold slack, specify timing constraints in the Intel® Quartus® Prime software.
Disk Space
By default, DSE II saves all the compilation data. You can save disk space by limiting the type of files that you want to save after a compilation finishes. These settings are in the Exploration page, Results section.
Reports
DSE II has reporting tools that help you quickly determine important design metrics, such as worse-case slack, across all exploration points.
DSE II provides a performance data report for all points it explores and saves the information in a project-name.dse.rpt file in the project directory. DSE II archives the settings of the exploration points in Intel® Quartus® Prime Archive Files (.qar).
Performing a Design Exploration with the DSE II Utility
This description covers the type of settings that you need to define when you want to run a design exploration. For details about all the options available in the GUI, refer to the Intel® Quartus® Prime Help.
To perform a design exploration with the DSE II tool:
-
Start the DSE II tool.
If you have an open project in the Intel® Quartus® Prime software and launch DSE II, a dialog box appears asking if you want to close the Intel® Quartus® Prime software. Click Yes.
- In the Project page, specify the project and revision that you want to explore.
- In the Setup page, specify whether you want to perform a local or a remote exploration, and set up the job launch.
- In the Exploration page, specify optimization settings and goals.
- When the configuration is complete, click Start.
Design Optimization Overview Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.05.07 | 18.0.0 |
|
2017.11.06 | 17.1.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.03 | 16.0.0 | Removed statements about serial equivalence when using multiple processors. |
2015.11.02 | 15.1.0 | Changed instances of Quartus II to Quartus Prime. |
2014.12.15 | 14.1.0 |
|
June 2014 | 14.0.0 | Updated format. |
November 2013 | 13.1.0 | Minor changes for HardCopy. |
May 2013 | 13.0.0 | Added the information about initial compilation requirements. This section was moved from the Area Optimization chapter of the Intel® Quartus® Prime Handbook. Minor updates to delineate division of Timing and Area optimization chapters. |
June 2012 | 12.0.0 | Removed survey link. |
November 2011 | 10.0.3 | Template update. |
December 2010 | 10.0.2 | Changed to new document template. No change to content. |
August 2010 | 10.0.1 | Corrected link |
July 2010 | 10.0.0 | Initial release. Chapter based on topics and text in Section III of volume 2. |
Optimizing the Design Netlist
This chapter describes how you can use the Intel® Quartus® Prime Netlist Viewers to analyze and debug your designs.
As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize, and constrain your design is critical. With today’s advanced designs, several design engineers are involved in coding and synthesizing different design blocks, making it difficult to analyze and debug the design. The Intel® Quartus® Prime RTL Viewer and Technology Map Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
When to Use the Netlist Viewers: Analyzing Design Problems
You can use the Netlist Viewers to analyze and debug your design. The following simple examples show how to use the RTL Viewer and Technology Map Viewer to analyze problems encountered in the design process.
Using the RTL Viewer is a good way to view your initial synthesis results to determine whether you have created the necessary logic, and that the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer to check your design visually before simulation or other verification processes. Catching design errors at this early stage of the design process can save you valuable time.
If you see unexpected behavior during verification, use the RTL Viewer to trace through the netlist and ensure that the connections and logic in your design are as expected. Viewing your design helps you find and analyze the source of design problems. If your design looks correct in the RTL Viewer, you know to focus your analysis on later stages of the design process and investigate potential timing violations or issues in the verification flow itself.
You can use the Technology Map Viewer to look at the results at the end of Analysis and Synthesis. If you have compiled your design through the Fitter stage, you can view your post‑mapping netlist in the Technology Map Viewer (Post-Mapping) and your post‑fitting netlist in the Technology Map Viewer. If you perform only Analysis and Synthesis, both the Netlist Viewers display the same post‑mapping netlist.
In addition, you can use the RTL Viewer or Technology Map Viewer to locate the source of a particular signal, which can help you debug your design. Use the navigation techniques described in this chapter to search easily through your design. You can trace back from a point of interest to find the source of the signal and ensure the connections are as expected.
The Technology Map Viewer can help you locate post‑synthesis nodes in your netlist and make assignments when optimizing your design. This functionality is useful when making a multicycle clock timing assignment between two registers in your design. Start at an I/O port and trace forward or backward through the design and through levels of hierarchy to find nodes of interest, or locate a specific register by visually inspecting the schematic.
Throughout your FPGA design, debug, and optimization stages, you can use all of the netlist viewers in many ways to increase your productivity while analyzing a design.
Intel Quartus Prime Design Flow with the Netlist Viewers
Click the link in the preprocessor process box to go to the Settings > Compilation Process Settings page where you can turn on the Run Netlist Viewers preprocessing during compilation option. If you turn this option on, the preprocessing becomes part of the full project compilation flow and the Netlist Viewer opens immediately without displaying the preprocessing dialog box.
This figure shows how Netlist Viewers fit into the basic Intel® Quartus® Prime design flow.
Before the Netlist Viewer can run the preprocessor stage, you must compile your design:
- To open the RTL Viewer first perform Analysis and Elaboration.
- To open the Technology Map Viewer (Post-Fitting) or the Technology Map Viewer (Post‑Mapping), first perform Analysis and Synthesis.
- Therefore, if you make a design change that causes an error during Analysis and Elaboration, you cannot view the netlist for the new design files, but you can still see the results from the last successfully compiled version of the design files.
- If you receive an error during compilation and you have not yet successfully run the appropriate compilation stage for your project, the Netlist Viewer cannot be displayed; in this case, the Intel® Quartus® Prime software issues an error message when you try to open the Netlist Viewer.
RTL Viewer Overview
You can view results after Analysis and Elaboration for designs that use any supported Intel® Quartus® Prime design entry method, including Verilog HDL Design Files (.v), SystemVerilog Design Files (.sv), VHDL Design Files (.vhd), AHDL Text Design Files (.tdf), or schematic Block Design Files (.bdf).
You can also view the hierarchy of atom primitives (such as device logic cells and I/O ports) for designs that generate Verilog Quartus Mapping File (.vqm) or Electronic Design Interchange Format (.edf) files through a synthesis tool.
- For designs synthesized with the Intel® Quartus® Prime Pro Edition synthesis, this view shows how the Intel® Quartus® Prime software interprets the design files.
- For designs synthesized with a third-party synthesis tool, this view shows the netlist that the synthesis tool generates.
To run the RTL Viewer for a Intel® Quartus® Prime project, first analyze the design to generate an RTL netlist. To analyze the design and generate an RTL netlist, click Processing > Start > Start Analysis & Elaboration. You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Intel® Quartus® Prime compilation flow.
To open the RTL Viewer, click Tools > Netlist Viewers > RTL Viewer.
Maximizing Readability in RTL Viewer
While displaying a design, the RTL Viewer optimizes the netlist to maximize readability:
- Removes logic with no fan-out (unconnected output) or fan-in (unconnected inputs) from the display.
- Hides default connections such as VCC and GND.
- Groups pins, nets, wires, module ports, and certain logic into buses where appropriate.
- Groups constant bus connections.
- Displays values in hexadecimal format.
- Converts NOT gates into bubble inversion symbols in the schematic.
- Merges chains of equivalent combinational gates into a single gate; for example, a 2-input AND gate feeding a 2-input AND gate is converted to a single 3-input AND gate.
Running the RTL Viewer
To run the RTL Viewer for an Intel® Quartus® Prime project:
-
Analyze the design to generate an RTL netlist by clicking Processing > Start > Start Analysis & Elaboration.
You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Intel® Quartus® Prime compilation flow.
- Open the RTL Viewer by clicking Tools > Netlist Viewers > RTL Viewer.
Technology Map Viewer Overview
The Technology Map Viewer shows the hierarchy of atom primitives (such as device logic cells and I/O ports) in the design. For supported device families, you can also view internal registers and look-up tables (LUTs) inside logic cells (LCELLs), and registers in I/O atom primitives.
Where possible, the Intel® Quartus® Prime software maintains the port names of each hierarchy throughout synthesis. However, the software may change or remove port names from the design. For example, the software removes ports that are unconnected or driven by GND or VCC during synthesis. If a port name changes, the software assigns a related user logic name in the design or a generic port name such as IN1 or OUT1.
You can view Intel® Quartus® Prime technology-mapped results after synthesis, fitting, or timing analysis. To run the Technology Map Viewer for a Intel® Quartus® Prime project, on the Processing menu, point to Start and click Start Analysis & Synthesis to synthesize and map the design to the target technology. At this stage, the Technology Map Viewer shows the same post-mapping netlist as the Technology Map Viewer (Post‑Mapping). You can also perform a full compilation, or any process that includes the synthesis stage in the compilation flow.
For designs that completed the Fitter stage, the Technology Map Viewer shows how the Fitter changed the netlist through physical synthesis optimizations, while the Technology Map Viewer (Post‑Mapping) shows the post-mapping netlist. If you have completed the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer.
To open the Technology Map Viewer, click Tools > Netlist Viewers > Technology Map Viewer (Post-Fitting) or Technology Map Viewer (Post Mapping).
Netlist Viewer User Interface
The RTL Viewer and Technology Map Viewer each consist of these main parts:
- The Netlist Navigator pane—displays a representation of the project hierarchy.
- The Find pane—allows you to find and locate specific design elements in the schematic view.
- The Properties pane displays the properties of the selected block when you select Properties from the shortcut menu.
- The schematic view—displays a graphical representation of the internal structure of the design.

Netlist Viewers also contain a toolbar that provides tools to use in the schematic view.
- Use the Back and Forward buttons to switch between schematic views. You can go forward only if you have not made any changes to the view since going back. These commands do not undo an action, such as selecting a node. The Netlist Viewer caches up to ten actions including filtering, hierarchy navigation, netlist navigation, and zoom actions.
- The Refresh button to restore the schematic view and optimizes the layout. Refresh does not reload the database if you change the design and recompile.
- Click the Find button opens and closes the Find pane.
- Click the Selection Tool and Zoom Tool buttons to alternate between the selection mode and zoom mode.
- Click the Fit in Page button resets the schematic view to encompass the entire design.
- Use the Hand Tool to change the focus of the viewer without changing the perspective.
- Click the Area Selection Tool to drag a selection box around ports, pins, and nodes in an area.
- Click the Netlist Navigator button to open or close the Netlist Navigator pane.
- Click the Color Settings button to open the Colors pane where you can customize the Netlist Viewer color scheme.
- Click the Display Settings
button to open the Display pane where you can
specify the following settings:
- Show full name or Show only <n> characters. You can specify this separately for Node name, Port name, Pin name, or Bus name.
- Turn Show timing info on or off.
- Turn Show node type on or off.
- Turn Show constant value on or off.
- Turn Show flat nets on or off.
Figure 4. Display Settings - The Bird's Eye View button opens the Bird's Eye View window which displays a miniature version of the design and allows you to navigate within the design and adjust the magnification in the schematic view quickly.
- The Show/Hide Instance Pins button can alternate the display of instance pins not displayed by functions such as cross-probing between a Netlist Viewer and Timing Analyzer. You can also use this button to hide unconnected instance pins when filtering a node results in large numbers of unconnected or unused pins. The Netlist Viewer hides Instance pins by default.
- If the Netlist Viewer display encompasses several pages, the Show Netlist on One Page button resizes the netlist view to a single page. This action can make netlist tracing easier.
You can have only one RTL Viewer, one Technology Map Viewer (Post-Fitting), and one Technology Map Viewer (Post-Mapping) window open at the same time, although each window can show multiple pages, each with multiple tabs. For example, you cannot have two RTL Viewer windows open at the same time.
Netlist Navigator Pane
The Netlist Navigator pane allows you to traverse through the design hierarchy to view the logic schematic for each level. You can also select an element in the Netlist Navigator to highlight in the schematic view.
For each module in the design hierarchy, the Netlist Navigator pane displays the applicable elements listed in the following table. Click the “+” icon to expand an element.
Elements | Description |
---|---|
Instances | Modules or instances in the design that can be expanded to lower hierarchy levels. |
Primitives |
Low-level nodes that cannot be expanded to any lower hierarchy level. These primitives include:
In the Technology Map Viewer, you can view the internal implementation of certain atom primitives, but you cannot traverse into a lower-level of hierarchy. |
Ports |
The I/O ports in the current level of hierarchy.
|
Properties Pane

The Properties pane contains tabs with the following information about the selected node:
- The Fan-in tab displays theInput port and Fan-in Node.
- The Fan-out tab displays theOutput port and Fan-out Node.
- The Parameters tab displays the Parameter Name and Values of an instance.
- The Ports tab displays the Port Name and Constant value (for example, VCC or GND). The following table lists the possible values of a port:
Value | Description |
---|---|
VCC |
The port is not connected and has VCC value (tied to VCC) |
GND | The port is not connected and has GND value (tied to GND) |
-- | The port is connected and has value (other than VCC or GND) |
Unconnected | The port is not connected and has no value (hanging) |
If the selected node is an atom primitive, the Properties pane displays a schematic of the internal logic.
Netlist Viewers Find Pane
You can narrow the range of the search process by setting the following options in the Find pane:
- Click Browse in the Find pane to specify the hierarchy level of the search. In the Select Hierarchy Level dialog box, select the particular instance you want to search.
- Turn on the Include subentities option to include child hierarchies of the parent instance during the search.
- Click Options to open the Find Options dialog box. Turn on Instances, Nodes, Ports, or any combination of the three to further refine the parameters of the search.
When you click the List button, a progress bar appears below the Find box.
All results that match the criteria you set are listed in a table. When you double‑click an item in the table, the related node is highlighted in red in the schematic view.
Schematic View
The RTL Viewer and Technology Map Viewer attempt to display schematic in a single page view by default. If the schematic crosses over to several pages, you can highlight a net and use connectors to trace the signal in a single page.
Display Schematics in Multiple Tabbed View
With multiple tabbed view, schematics can be displayed in different tabs. Selection is independent between tabbed views, but selection in the tab in focus is synchronous with the Netlist Navigator pane.
To create a new blank tab, click the New Tab button at the end of the tab row . You can now drag a node from the Netlist Navigator pane into the schematic view.
Right-click in a tab to see a shortcut menu to perform the following actions:
- Create a blank view with New Tab
- Create a Duplicate Tab of the tab in focus
- Choose to Cascade Tabs
- Choose to Tile Tabs
- Choose Close Tab to close the tab in focus
- Choose Close Other Tabs to close all tabs except the tab in focus
Schematic Symbols
Symbol | Description |
---|---|
I/O Ports |
An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or bidirectional pin when viewing the top‑level hierarchy. The symbol can also represent a bus. Only one wire is shown connected to the bidirectional symbol, representing the input and output paths. Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols appear on the right‑most side of the schematic. |
I/O Connectors |
An input or output connector, representing a net that comes from another page of the same hierarchy. To go to the page that contains the source or the destination, double-click the connector to jump to the appropriate page. |
OR, AND, XOR Gates |
An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble symbol) on an input or output port indicates the port is inverted. |
MULTIPLEXER |
A multiplexer primitive with a selector port that selects between port 0 and port 1. A multiplexer with more than two inputs is displayed as an operator. |
BUFFER |
A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port. Other buffers without an enable port include LCELL, SOFT, and GLOBAL. The NOT gate and EXP expander buffers use this symbol without an enable port and with an inverted output port. |
LATCH |
A latch/DFF (data flipflop) primitive. A DFF has the same ports
as a latch and a clock trigger. The other flipflop primitives are similar:
|
Atom Primitive |
An atom primitive. The symbol displays the atom name, the port names, and the atom type. The blue shading indicates an atom primitive for which you can view the internal details. |
Other Primitive |
Any primitive that does not fall into the previous categories. Primitives are low-level nodes that cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive or operator type, and its name. |
Instance |
An instance in the design that does not correspond to a primitive or operator (a user‑defined hierarchy block). The symbol displays the port name and the instance name. |
Encrypted Instance |
A user-defined encrypted instance in the design. The symbol displays the instance name. You cannot open the schematic for the lower-level hierarchy, because the source design is encrypted. |
RAM |
A synchronous memory instance with registered inputs and optionally registered outputs. The symbol shows the device family and the type of memory block. This figure shows a true dual-port memory block in a Stratix M-RAM block. |
Constant |
A constant signal value that is highlighted in gray and displayed in hexadecimal format by default throughout the schematic. |
Symbol | Description |
---|---|
|
An adder operator: OUT = A + B |
|
A multiplier operator: OUT = A ¥ B |
|
A divider operator: OUT = A / B |
|
Equals |
|
A left shift operator: OUT = (A << COUNT) |
|
A right shift operator: OUT = (A >> COUNT) |
|
A modulo operator: OUT = (A%B) |
|
A less than comparator: OUT = (A<:B:A>B) |
|
A multiplexer: OUT = DATA [SEL] The data range size is 2sel range size |
|
A selector: A multiplexer with one-hot select input and more than two input signals |
|
A binary number decoder: OUT = (binary_number (IN) == x) for x = 0 to |
Select Items in the Schematic View
To select an item in the schematic view, ensure that the Selection Tool is enabled in the Netlist Viewer toolbar. Click an item in the schematic view to highlight in red.
Select multiple items by pressing the Shift key while selecting with the mouse.
Items selected in the schematic view are automatically selected in the Netlist Navigator pane. The folder then expands automatically if it is required to show the selected entry; however, the folder does not collapse automatically when you deselected the entries.
When you select a hierarchy box, node, or port in the schematic view, the Schematic View highlights the item in red, but not the connecting nets. When you select a net (wire or bus) in the schematic view, the Schematic View highlights all connected nets in red.
Once you select an item, you can perform different actions on it based on the contents of the shortcut menu which appears when you right-click your selection.
Shortcut Menu Commands in the Schematic View
If the selected item is a node, you see the following options:
- Click Expand to Upper Hierarchy to displays the parent hierarchy of the node in focus.
- Click Copy ToolTip to copy the selected item name to the clipboard. This command does not work on nets.
- Click Hide Selection to remove the selected item from the schematic view. This command does not delete the item from the design, merely masks it in the current view.
- Click Filtering to display a sub-menu with options for filtering your selection.
Filtering in the Schematic View
You can filter a netlist by selecting hierarchy boxes, nodes, or ports of a node, that are part of the path you want to see. The following filter commands are available:
- Sources—displays the sources of the selection.
- Destinations—displays the destinations of the selection.
- Sources & Destinations—displays the sources and destinations of the selection.
- Selected Nodes—displays only the selected nodes.
- Between Selected Nodes—displays nodes and connections in the path between the selected nodes.
- Bus Index—Displays the sources or destinations for one or more indexes of an output or input bus port.
-
Filtering Options—Displays the Filtering Options dialog box:
- Stop filtering at register—Turning on this option directs the Netlist Viewer to filter out to the nearest register boundary.
- Filter across hierarchies—Turning on this option directs the Netlist Viewer to filter across hierarchies.
- Maximum number of hierarchy levels—Sets the maximum number of hierarchy levels that the schematic view can display.
To filter a netlist, select a hierarchy box, node, port, net, or state node, right-click in the window, point to Filter and click the appropriate filter command. The Netlist Viewer generates a new page showing the netlist that remains after filtering.
View Contents of Nodes in the Schematic View
You can view LUTs, registers, and logic gates. You can also view the implementation of RAM and DSP blocks in certain devices in the RTL Viewer or Technology Map Viewer. In the Technology Map Viewer, you can view the contents of primitives to see their underlying implementation details.




You can double-click objects in the Connectivity Details window to navigate to them quickly. If the plus symbol appears, you can further unwrap objects in the view. This can be very useful when tracing a signal in a complex netlist.
Moving Nodes in the Schematic View
To move a node from one area of the netlist to another, select the node and hold down the Shift key. Legal placements appear as shaded areas within the hierarchy. Click to drop the selected node.

To restore the schematic view to its default arrangement, right-click and click Refresh.
View LUT Representations in the Technology Map Viewer
You can view the LUT representations in the following three tabs in the Properties dialog box:
- The Schematic tab—the equivalent gate representations of the LUT.
- The Truth Table tab—the truth table representations.
Zoom Controls
By default, the Netlist Viewer displays most pages sized to fit in the window. If the schematic page is very large, the schematic is displayed at the minimum zoom level, and the view is centered on the first node. Click Zoom In to view the image at a larger size, and click Zoom Out to view the image (when the entire image is not displayed) at a smaller size. The Zoom command allows you to specify a magnification percentage (100% is considered the normal size for the schematic symbols).
You can use the Zoom Tool on the Netlist Viewer toolbar to control magnification in the schematic view. When you select the Zoom Tool in the toolbar, clicking in the schematic zooms in and centers the view on the location you clicked. Right‑click in the schematic to zoom out and center the view on the location you clicked. When you select the Zoom Tool, you can also zoom into a certain portion of the schematic by selecting a rectangular box area with your mouse cursor. The schematic is enlarged to show the selected area.
Within the schematic view, you can also use the following mouse gestures to zoom in on a specific section:
- zoom in—Dragging a box around an area starting in the upper-left and dragging to the lower right zooms in on that area.
- zoom -0.5—Dragging a line from lower-left to upper-right zooms out 0.5 levels of magnification.
- zoom 0.5—Dragging a line from lower-right to upper-left zooms in 0.5 levels of magnification.
- zoom fit—Dragging a line from upper-right to lower-left fits the schematic view in the page.
Navigating with the Bird's Eye View
Viewing the entire schematic can be useful when debugging and tracing through a large netlist. The Intel® Quartus® Prime software allows you to quickly navigate to a specific section of the schematic using the Bird’s Eye View feature, which is available in the RTL Viewer and Technology Map Viewer.
The Bird’s Eye View shows the current area of interest:
- Select an area by clicking and dragging the indicator or right-clicking to form a rectangular box around an area.
- Click and drag the rectangular box to move around the schematic.
- Resize the rectangular box to zoom-in or zoom-out in the schematic view.
Partition the Schematic into Pages
When a hierarchy level is partitioned into multiple pages, the title bar for the schematic window indicates which page is displayed and how many total pages exist for this level of hierarchy. The schematic view displays this as Page <current page number> of <total number of pages>.
Follow Nets Across Schematic Pages
Cross-Probing to a Source Design File and Other Intel Quartus Prime Windows
You can select one or more hierarchy boxes, nodes, state nodes, or state transition arcs that interest you in the Netlist Viewer and locate the corresponding items in another applicable Intel® Quartus® Prime software window. You can then view and make changes or assignments in the appropriate editor or floorplan.
To locate an item from the Netlist Viewer in another window, right-click the items of interest in the schematic or state diagram, point to Locate, and click the appropriate command. The following commands are available:
- Locate in Assignment Editor
- Locate in Pin Planner
- Locate in Chip Planner
- Locate in Resource Property Editor
- Locate in Technology Map Viewer
- Locate in RTL Viewer
- Locate in Design File
The options available for locating an item depend on the type of node and whether it exists after placement and routing. If a command is enabled in the menu, it is available for the selected node. You can use the Locate in Assignment Editor command for all nodes, but assignments might be ignored during placement and routing if they are applied to nodes that do not exist after synthesis.
The Netlist Viewer automatically opens another window for the appropriate editor or floorplan and highlights the selected node or net in the newly opened window. You can switch back to the Netlist Viewer by selecting it in the Window menu or by closing, minimizing, or moving the new window.
Cross-Probing to the Netlist Viewers from Other Intel Quartus Prime Windows
You can locate nodes between the RTL Viewer and Technology Map Viewer, and you can locate nodes in the RTL Viewer and Technology Map Viewer from the following Intel® Quartus® Prime software windows:
- Project Navigator
- Timing Closure Floorplan
- Chip Planner
- Resource Property Editor
- Node Finder
- Assignment Editor
- Messages Window
- Compilation Report
- Timing Analyzer (supports the Technology Map Viewer only)
To locate elements in the Netlist Viewer from another Intel® Quartus® Prime window, select the node or nodes in the appropriate window; for example, select an entity in the Entity list on the Hierarchy tab in the Project Navigator, or select nodes in the Timing Closure Floorplan, or select node names in the From or To column in the Assignment Editor. Next, right-click the selected object, point to Locate, and click Locate in RTL Viewer or Locate in Technology Map Viewer. After you click this command, the Netlist Viewer opens, or is brought to the foreground if the Netlist Viewer is open.
The Netlist Viewer shows the selected nodes and, if applicable, the connections between the nodes. The display is similar to what you see if you right‑click the object, then click Filter > Selected Nodes using Filter across hierarchy. If the nodes cannot be found in the Netlist Viewer, a message box displays the message: Can’t find requested location.
Viewing a Timing Path
When you locate the timing path from the Timing Analyzer to the Technology Map Viewer, the interconnect and cell delay associated with each node appears on top of the schematic symbols. The total slack of the selected timing path appears in the Page Title section of the schematic.
- To open the report from the Compilation Report Table of Contents, click Timing Analyzer GUI > Report Timing, and double-click the timing corner.
- To open the report from the Timing Analyzer, open the Report Timing folder in the Report pane, and double-click the timing corner.
- In the Summary of Paths tab, right-click a row in the table and select Locate Path > Locate in Technology Map Viewer. In the Technology Map Viewer, the schematic page displays the nodes along the timing path with a summary of the total delay.
Optimizing the Design Netlist Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.03 | 16.0.0 | Removed Schematic Viewer topic. |
2015.11.02 | 15.1.0 |
Added Schematic Viewer topic for viewing stage snapshots. Added information for the following new features and feature
updates:
|
2014.06.30 | 14.0.0 | Added Show Netlist on One Page and show/Hide Instance Pins commands. |
November 2013 | 13.1.0 |
Removed HardCopy device information. Reorganized and migrated to new template. Added support for new Netlist viewer. |
November 2012 | 12.1.0 | Added sections to support Global Net Routing feature. |
June 2012 | 12.0.0 | Removed survey link. |
November 2011 | 10.0.2 | Template update. |
December 2010 | 10.0.1 | Changed to new document template. |
July 2010 | 10.0.0 |
|
November 2009 | 9.1.0 |
|
March 2009 | 9.0.0 |
|
November 2008 | 8.1.0 | Changed page size to 8.5” × 11” |
May 2008 | 8.0.0 |
|
Netlist Optimizations and Physical Synthesis
Options | Location/Description |
---|---|
Enable physical synthesis options. | Assignments > Settings > Compiler Settings > Advanced Settings (Fitter). Physical synthesis optimizations apply at different stages of the compilation flow, either during synthesis, fitting, or both. |
Enable netlist optimization options. | Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). Netlist optimizations operate with the atom netlist of your design, which describes a design in terms of specific primitives. An atom netlist file can be an Electronic Design Interchange Format (.edf) file generated by a third-party synthesis tool. Intel® Quartus® Prime synthesis generates and internally uses the atom netlist internally |
Physical Synthesis Optimizations
The following sections describe the physical synthesis optimizations available in the Intel® Quartus® Prime software, and how they can help improve performance and fitting for the selected device.
Enabling Physical Synthesis Optimization
To enable physical synthesis options:
- Click Assignments > Settings > Compiler Settings.
- To enable retiming, combinational optimization, and register duplication, click Advanced Settings (Fitter). Next, enable Physical Synthesis.
- View physical synthesis results in the Netlist Optimizations report.
Physical Synthesis Options
Option | Description |
---|---|
Advanced Physical Synthesis | Uses the physical synthesis engine to perform combinational and sequential optimization during fitting to improve circuit performance. |
Netlist Optimizations | You can use the Assignment Editor to apply the Netlist Optimizations logic option. Use this option to disable physical synthesis optimizations for parts of your design. |
Allow Register Duplication |
Allows the Compiler to duplicate registers to improve design performance. When you enable this option, the Compiler copies registers and moves some fan-out to this new node. This optimization improves routability and can reduce the total routing wire in nets with many fan-outs. If you disable this option, this disables optimizations that retime registers. This setting affects Analysis & Synthesis and the Fitter. |
Allow Register Merging |
Allows the Compiler to remove registers that are identical to other registers in the design. When you enable this option, in cases where two registers generate the same logic, the Compiler deletes one register, and the remaining registers fan-out to the deleted register's destinations. This option is useful if you want to prevent the Compiler from removing intentional use of duplicate registers. If you disable register merging, the Compiler disables optimizations that retime registers. This setting affects Analysis & Synthesis and the Fitter. |
Applying Netlist Optimizations
You may have to experiment with available options to see which combination of settings works best for a particular design. Refer to the messages in the compilation report to see the magnitude of improvement with each option, and to help you decide whether you should turn on a given option or specific effort level.
Turning on more netlist optimization options can result in more changes to the node names in the design; bear this in mind if you are using a verification flow, such as the Signal Tap Logic Analyzer or formal verification that requires fixed or known node names.
To find the best results, you can use the Intel® Quartus® Prime Design Space Explorer II (DSE) to apply various sets of netlist optimization options.
WYSIWYG Primitive Resynthesis
The Perform WYSIWYG primitive resynthesis option directs the Intel® Quartus® Prime software to un-map the logic elements (LEs) in an atom netlist to logic gates, and then re-map the gates back to Intel-specific primitives. Third-party synthesis tools generate either an .edf or .vqm atom netlist file using Intel-specific primitives. When you turn on the Perform WYSIWYG primitive resynthesis option, the Intel® Quartus® Prime software uses device-specific techniques during the re-mapping process. This feature re-maps the design using the Optimization Technique specified for your project (Speed, Area, or Balanced).
The Perform WYSIWYG primitive resynthesis option unmaps and remaps only logic cells, also referred to as LCELL or LE primitives, and regular I/O primitives (which may contain registers). Double data rate (DDR) I/O primitives, memory primitives, digital signal processing (DSP) primitives, and logic cells in carry chains are not remapped. This process does not process logic specified in an encrypted .vqm file or an .edf file, such as third-party intellectual property (IP).
The Perform WYSIWYG primitive resynthesisoption can change node names in the .vqm file or .edf file from your third-party synthesis tool, because the primitives in the atom netlist are broken apart and then re-mapped by the Intel® Quartus® Prime software. The re-mapping process removes duplicate registers. Registers that are not removed retain the same name after re-mapping.
Any nodes or entities that have the Netlist Optimizations logic option set to Never Allow are not affected during WYSIWYG primitive resynthesis. You can use the Assignment Editor to apply the Netlist Optimizations logic option. This option disables WYSIWYG resynthesis for parts of your design.
If you use the Intel® Quartus® Prime software to synthesize your design, you can use the Preserve Register (preserve) and Keep Combinational Logic (keep) attributes to maintain certain nodes in the design.

Scripting Support
quartus_sh --qhelp
You can specify many of the options described in this section on either an instance or global level, or both.
Use the following Tcl command to make a global assignment:
set_global_assignment -name <QSF variable name> <value>
Use the following Tcl command to make an instance assignment:
set_instance_assignment -name <QSF variable name> <value> \ -to <instance name>
Synthesis Netlist Optimizations
Setting Name | Intel® Quartus® Prime Settings File Variable Name | Values | Type |
---|---|---|---|
Perform WYSIWYG Primitive Resynthesis | ADV_NETLIST_OPT_SYNTH_WYSIWYG_ REMAP | ON, OFF | Global, Instance |
Optimization Mode | OPTIMIZATION_MODE | BALANCED HIGH PERFORMANCE EFFOR AGGRESSIVE PERFORMANCE | Global, Instance |
Power-Up Don’t Care | ALLOW_POWER_UP_DONT_CARE | ON, OFF | Global |
Physical Synthesis Optimizations
Setting Name | Intel® Quartus® Prime Settings File Variable Name | Values | Type |
---|---|---|---|
Advanced Physical Synthesis | ADVANCED_PHYSICAL_SYNTHESIS | ON, OFF | Global |
Netlist Optimizations and Physical Synthesis Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 | Removed reference to unsupported CASCADE buffer from "Optimize IOC Register Placement for Timing Logic Option" topic. |
2018.05.07 | 18.0.0 | Removed topic: Isolating a Partition Netlist. |
2017.11.06 | 17.1.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.02 | 16.0.0 |
|
2015.11.02 | 15.1.0 |
|
2014.12.15 | 14.1.0 |
|
June 2014 | 14.0.0 | Updated format. |
November 2013 | 13.1.0 | Removed HardCopy device information. |
June 2012 | 12.0.0 | Removed survey link. |
November 2011 | 10.0.2 | Template update. |
December 2010 | 10.0.1 | Template update. |
July 2010 | 10.0.0 |
|
November 2009 | 9.1.0 |
|
March 2009 | 9.0.0 |
|
November 2008 | 8.1.0 | Changed to 8½” × 11” page size. No change to content. |
May 2008 | 8.0.0 |
|
Area Optimization
Resource Utilization Information
Determining device utilization provides useful information regardless of whether the design achieved a successful fit. If the compilation results in a no-fit error, resource utilization information helps to analyze the fitting problems in the design. If the fitting is successful, this information allows you to determine if design changes introduce fitting difficulties. Additionally, you can determine the impact of the resource utilization in the timing performance.
The Compilation Report provides information about resource usage.
Flow Summary Report
The Flow Summary section of the compilation report indicates whether the design exceeds the available device resources, and reports resource utilization, including pins, memory bits, digital signal processing (DSP) blocks, and phase-locked loops (PLLs).

The Fitter can spread logic throughout the device, which may lead to higher overall utilization.
As the device fills up, the Fitter automatically searches for logic functions with common inputs to place in one ALM. The number of packed registers also increases. Therefore, a design that has high overall utilization might still have space for extra logic if the logic and registers can be packed together more tightly. In those cases, you can benefit by a report that provides more details.
Fitter Reports
In the Fitter section of the compilation report, reports under Resource Section provide detailed resource information.
The Fitter Resource Usage Summary report breaks down the logic utilization information and provides additional resource information, including the number of bits in each type of memory block. This panel also contains a summary of the usage of global clocks, PLLs, DSP blocks, and other device-specific resources.
Analysis and Synthesis Reports
For designs synthesized with the Intel® Quartus® Prime synthesis engine, you can see reports describing optimizations that occurred during compilation.
For example, in the Analysis & Synthesis section, Optimization Results folder, you can find a list of registers removed during synthesis. With this report you can estimate resource utilization for partial designs so you make sure that registers were not removed due to missing connections with other parts of the design.
Compilation Messages
If the reports show routing resource usage lower than 100% but the design does not fit, either routing resources are insufficient or the design contains invalid assignments. In either case, the Compiler generates a message in the Processing tab of the Messages window describing the problem.
If the Fitter finishes unsuccessfully and runs much faster than on similar designs, a resource might be over-utilized or there might be an illegal assignment.
If the Intel® Quartus® Prime software takes too long to run when compared to similar designs possibly the Compiler is not able to find valid placement or route. In the Compilation Report, look for errors and warnings that indicate these types of problems.
The Chip Planner can help you find areas of the device that have routing congestion for specific types of routing resources. If you find areas with very high congestion, analyze the cause of the congestion. Issues such as high fan-out nets not using global resources, an improperly chosen optimization goal (speed versus area), very restrictive floorplan assignments, or the coding style can cause routing congestion. After you identify the cause, modify the source or settings to reduce routing congestion.
Optimizing Resource Utilization
- Optimize resource utilization—Ensure that you have already set the basic constraints
- I/O timing optimization—Optimize I/O timing after you optimize resource utilization and your design fits in the desired target device
- Register-to-register timing optimization
Resource Utilization Issues Overview
- Issues relating to I/O pin utilization or placement, including dedicated I/O blocks such as PLLs or LVDS transceivers.
- Issues relating to logic utilization or placement, including logic cells containing registers and LUTs as well as dedicated logic, such as memory blocks and DSP blocks.
- Issues relating to routing.
I/O Pin Utilization or Placement
Guideline: Modify Pin Assignments or Choose a Larger Package
If the design fits when all pin assignments are ignored or when several pin assignments are ignored or moved, you might have to modify the pin assignments for the design or select a larger package.
If the design fails to fit because insufficient I/Os pins are available, a larger device package (which can be the same device density) that has more available user I/O pins can result in a successful fit.
Logic Utilization or Placement
Guideline: Optimize Source Code
If your design does not fit into available logic elements (LEs) or ALMs, but you have unused memory or DSP blocks, check if you have code blocks in your design that describe memory or DSP functions that are not being inferred and placed in dedicated logic. You might be able to modify your source code to allow these functions to be placed into dedicated memory or DSP resources in the target device.
Ensure that your state machines are recognized as state machine logic and optimized appropriately in your synthesis tool. State machines that are recognized are generally optimized better than if the synthesis tool treats them as generic logic. In the Intel® Quartus® Prime software, you can check for the State Machine report under Analysis & Synthesis in the Compilation Report. This report provides details, including the state encoding for each state machine that was recognized during compilation. If your state machine is not being recognized, you might have to change your source code to enable it to be recognized.
Guideline: Optimize Synthesis for Area, Not Speed
First, ensure that the device and timing constraints are set correctly in the synthesis tool. Particularly when area utilization of the design is a concern, ensure that you do not over-constrain the timing requirements for the design. Synthesis tools try to meet the specified requirements, which can result in higher device resource usage if the constraints are too aggressive.
If resource utilization is an important concern, you can optimize for area instead of speed.
- If you are using Intel® Quartus® Prime synthesis, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) and select Balanced or Area for the Optimization Technique.
- If you want to reduce area for specific modules in the design using the Area or Speed setting while leaving the default Optimization Technique setting at Balanced, use the Assignment Editor.
- You can also turn on the Speed Optimization Technique for Clock Domains logic option to optimize for speed all combinational logic in or between the specified clock domains.
- In some synthesis tools, not specifying an fMAX requirement can result in less resource utilization.
Optimizing for area or speed can affect the register-to-register timing performance.
The Intel® Quartus® Prime software provides additional attributes and options that can help improve the quality of the synthesis results.
Guideline: Restructure Multiplexers
Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting
Guideline: Use Register Packing
Guideline: Flatten the Hierarchy During Synthesis
Guideline: Re-target Memory Blocks
For memory blocks created with the Parameter Editor, edit the RAM block type to target a new memory block size.
The Compiler can also infer ROM and RAM memory blocks from the HDL code, and the synthesis engine can place large shift registers into memory blocks by inferring the Shift register (RAM-based) IP core. When you turn off this inference in the synthesis tool, the synthesis engine places the memory or shift registers in logic instead of memory blocks. Also, turning off this inference prevents registers from being moved into RAM, improving timing performance,
Depending on the synthesis tool, you can also set the RAM block type for inferred memory blocks. In Intel® Quartus® Prime synthesis, set the ramstyle attribute to the desired memory type for the inferred RAM blocks. Alternatively, set the option to logic to implement the memory block in standard logic instead of a memory block.
Consider the Resource Utilization by Entity report in the report file and determine whether there is an unusually high register count in any of the modules. Some coding styles prevent the Intel® Quartus® Prime software from inferring RAM blocks from the source code because of the blocks’ architectural implementation, forcing the software to implement the logic in flip-flops. For example, an asynchronous reset on a register bank might make the register bank incompatible with the RAM blocks in the device architecture, so Compiler implements the register bank in flip-flops. It is often possible to move a large register bank into RAM by slight modification of associated logic.
Guideline: Use Physical Synthesis Options to Reduce Area
Guideline: Retarget or Balance DSP Blocks
If the DSP function was created with the parameter editor, open the parameter editor and edit the function so it targets logic cells instead of DSP blocks. The Intel® Quartus® Prime software uses the DEDICATED_MULTIPLIER_CIRCUITRY IP core parameter to control the implementation.
DSP blocks also can be inferred from your HDL code for multipliers, multiply-adders, and multiply-accumulators. You can turn off this inference in your synthesis tool. When you are using Intel® Quartus® Prime synthesis, you can disable inference by turning off the Auto DSP Block Replacement logic option for your entire project. Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). Turn off Auto DSP Block Replacement. Alternatively, you can disable the option for a specific block with the Assignment Editor.
The Intel® Quartus® Prime software also offers the DSP Block Balancing logic option, which implements DSP block elements in logic cells or in different DSP block modes. The default Auto setting allows DSP block balancing to convert the DSP block slices automatically as appropriate to minimize the area and maximize the speed of the design. You can use other settings for a specific node or entity, or on a project-wide basis, to control how the Intel® Quartus® Prime software converts DSP functions into logic cells and DSP blocks. Using any value other than Auto or Off overrides the DEDICATED_MULTIPLIER_CIRCUITRY parameter used in IP core variations.
Routing
Guideline: Set Auto Packed Registers to Sparse or Sparse Auto
Guideline: Set Fitter Aggressive Routability Optimizations to Always
If there is a significant imbalance between placement and routing time (during the first fitting attempt), it might be because of high wire utilization. Turning on the Fitter Aggressive Routability Optimizations option can reduce your compilation time.
On average, this option can save up to 6% wire utilization, but can also reduce performance by up to 4%, depending on the device.
Guideline: Increase Router Effort Multiplier
The Router Effort Multiplier controls how quickly the router tries to find a valid solution. The default value is 1.0 and legal values must be greater than 0.
- Numbers higher than 1 help designs that are difficult to route by increasing the routing effort.
- Numbers closer to 0 (for example, 0.1) can reduce router runtime, but usually reduce routing quality slightly.
Guideline: Remove Fitter Constraints
To resolve routing congestion caused by restrictive location constraints or Logic Lock region assignments, use the Routing Congestion task in the Chip Planner to locate routing problems in the floorplan, then remove any internal location or Logic Lock region assignments in that area. If your design still does not fit, the design is over-constrained. To correct the problem, remove all location and Logic Lock assignments and run successive compilations, incrementally constraining the design before each compilation. You can delete specific location assignments in the Assignment Editor or the Chip Planner. To remove Logic Lock assignments in the Chip Planner, in the Logic Lock Regions Window, or on the Assignments menu, click Remove Assignments. Turn on the assignment categories you want to remove from the design in the Available assignment categories list.
Guideline: Optimize Synthesis for Area, Not Speed
If resource utilization is an important concern, you can optimize for area instead of speed.
- If you are using Intel® Quartus® Prime synthesis, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) and select Balanced or Area for the Optimization Technique.
- If you want to reduce area for specific modules in your design using the Area or Speed setting while leaving the default Optimization Technique setting at Balanced, use the Assignment Editor.
- You can also use the Speed Optimization Technique for Clock Domains logic option to specify that all combinational logic in or between the specified clock domain(s) is optimized for speed.
- In some synthesis tools, not specifying an fMAX requirement can result in lower resource utilization.
Optimizing for area or speed can affect the register-to-register timing performance.
The Intel® Quartus® Prime software provides additional attributes and options that can help improve the quality of your synthesis results.
Guideline: Optimize Source Code
Guideline: Use a Larger Device
Scripting Support
-
To run the Help browser, type the following command at the command prompt:
quartus_sh --qhelp
You can specify many of the options described in this section either in an instance, or at a global level, or both.
-
Use the following Tcl command to make a global assignment:
set_global_assignment -name <QSF variable name> <value>
-
Use the following Tcl command to make an instance assignment:
set_instance_assignment -name <QSF variable name> <value> \ -to <instance name>
Initial Compilation Settings
Setting Name | .qsf File Variable Name | Values | Type |
---|---|---|---|
Placement Effort Multiplier | PLACEMENT_EFFORT_MULTIPLIER | Any positive, non-zero value | Global |
Router Effort Multiplier | ROUTER_EFFORT_MULTIPLIER | Any positive, non-zero value | Global |
Router Timing Optimization level | ROUTER_TIMING_OPTIMIZATION_LEVEL | NORMAL, MINIMUM, MAXIMUM | Global |
Final Placement Optimization | FINAL_PLACEMENT_OPTIMIZATION | ALWAYS, AUTOMATICALLY, NEVER | Global |
Resource Utilization Optimization Techniques
This table lists QSF assignments and applicable values for Resource Utilization Optimization settings:
Setting Name | .qsf File Variable Name | Values | Type |
---|---|---|---|
Auto Packed Registers | QII_AUTO_PACKED_REGISTERS | AUTO, OFF, NORMAL, MINIMIZE AREA, MINIMIZE AREA WITH CHAINS,SPARSE, SPARSE AUTO | Global, Instance |
Perform WYSIWYG Primitive Resynthesis | ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP | ON, OFF | Global, Instance |
Optimization Technique | OPTIMIZATION_TECHNIQUE | AREA, SPEED, BALANCED | Global, Instance |
Speed Optimization Technique for Clock Domains | SYNTH_CRITICAL_CLOCK | ON, OFF | Instance |
State Machine Encoding | STATE_MACHINE_PROCESSING | AUTO, ONE-HOT, GRAY, JOHNSON, MINIMAL BITS, ONE-HOT, SEQUENTIAL, USER-ENCODE | Global, Instance |
Auto RAM Replacement | AUTO_RAM_RECOGNITION | ON, OFF | Global, Instance |
Auto ROM Replacement | AUTO_ROM_RECOGNITION | ON, OFF | Global, Instance |
Auto Shift Register Replacement | AUTO_SHIFT_REGISTER_RECOGNITION | ON, OFF | Global, Instance |
Auto Block Replacement | AUTO_DSP_RECOGNITION | ON, OFF | Global, Instance |
Number of Processors for Parallel Compilation | NUM_PARALLEL_PROCESSORS | Integer between 1 and 16 inclusive, or ALL | Global |
Area Optimization Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.10.18 | 18.1.0 |
|
2018.09.24 | 18.1.0 |
|
2018.07.03 | 18.0.0 | Fixed typo and added links in topic Guideline: Retarget Memory Blocks. |
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.02 | 16.0.0 |
|
2015.11.02 | 15.1.0 | Changed instances of Quartus II to Intel Quartus Prime. |
2014.12.15 | 14.1.0 | Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings. |
June 2014 | 14.0.0 |
|
May 2013 | 13.0.0 | Initial release. |
Timing Closure and Optimization
Optimize Multi Corner Timing
In addition, designs targeting newer device families (with smaller process geometry) do not always present the slowest circuit performance at the highest operating temperature. The temperature at which the circuit is slowest depends on the selected device, the design, and the compilation results. The Intel® Quartus® Prime software manages this new dependency by providing newer device families with three different timing corners—Slow 85°C corner, Slow 0°C corner, and Fast 0°C corner. For other device families, two timing corners are available—Fast 0°C and Slow 85°C corner.
The Optimize multi-corner timing option directs the Fitter to meet timing requirements at all process corners and operating conditions. The resulting design implementation is more robust across process, temperature, and voltage variations. This option is on by default, and increases compilation time by approximately 10%.
When this option is off, the Fitter optimizes designs considering only slow-corner delays from the slow-corner timing model (slowest manufactured device for a given speed grade, operating in low-voltage conditions).
Critical Paths
The slack of a path determines its criticality; slack appears in the timing analysis report, which you can generate using the Timing Analyzer.
Design analysis for timing closure is a fundamental requirement for optimal performance in highly complex designs. The analytical capability of the Chip Planner helps you close timing on complex designs.
Viewing Critical Paths
Viewing critical paths in the Chip Planner shows why a specific path is failing. You can see if any modification in the placement can reduce the negative slack. To display paths in the floorplan, perform a timing analysis and display results on the Timing Analyzer.
Critical Chains
A critical chain reports the design paths that limit further register retiming optimization. The Intel® Quartus® Prime Pro Edition software provides the Hyper-Retimer critical chain reports to help you improve design performance. You can focus on higher level optimization, because the Hyper-Retimer uses Hyper-Registers to evenly balance slacks on all the registers in a critical chain.
For more information about improving design performance using the Hyper-Retimer critical chain reports, refer to the Interpreting Critical Chain Reports topic in the Intel® Stratix® 10 High-Performance Design Handbook.
Viewing Critical Chains
-
In the Retiming Limit Details Report:
This report is associated with the retiming stage in the Hyper Aware Design Flow, and is enabled by default.
-
In the Fast Forward Compilation Report:
The Fast Forward Compilation stage is optional, and disabled by default. You enable this stage from the Compilation Dashboard. Alternatively, start the task directly by clicking the Fast Forward Timing Closure Recommendations in the Compilations tasks.
- You can also graphically visualize the critical chains in the Technology Map Viewer. For more details, refer to Locate Critical Chains in the Intel® Stratix® 10 High-Performance Design Handbook .
Design Evaluation for Timing Closure
Review Compilation Results
Review Messages
Most designs that fail timing start out with other problems that the Fitter reports as warning messages during compilation. Determine what causes a warning message, and whether to fix or ignore the warning.
After reviewing the warning messages, review the informational messages. Take note of anything unexpected, for example, unconnected ports, ignored constraints, missing files, and assumptions or optimizations that the software made.
Evaluate Fitter Netlist Optimizations
Evaluate Optimization Results
Evaluate Resource Usage
Global and Non-Global Usage
The figure shows an example of inefficient use of a global clock. The highlighted line has a single fan-out from a global clock.
If you assign these resources to a Regional Clock, the Global Clock becomes available for another signal. You can ignore signals with an empty value in the Global Line Name column as the signal uses dedicated routing, and not a clock buffer.
The Non-Global High Fan-Out Signals report lists the highest fan-out nodes not routed on global signals.
Reset and enable signals appear at the top of the list.
If there is routing congestion in the design, and there are high fan-out non-global nodes in the congested area, consider using global or regional signals to fan-out the nodes, or duplicate the high fan-out registers so that each of the duplicates can have fewer fan-outs.
Use the Chip Planner to locate high fan-out nodes, to report routing congestion, and to determine whether the alternatives are viable.
Routing Usage

Average interconnect usage reports the average amount of interconnect that is used, out of what is available on the device. Peak interconnect usage reports the largest amount of interconnect used in the most congested areas.
Designs with an average value below 50% typically do not have any problems with routing. Designs with an average between 50-65% may have difficulty routing. Designs with an average over 65% typically have difficulty meeting timing unless the RTL tolerates a highly utilized chip. Peak values at or above 90% are likely to have problems with timing closure; a 100% peak value indicates that all routing in an area of the device has been used, so there is a high possibility of degradation in timing performance.
The figure shows the Report Routing Utilization report.

Wires Added for Hold
Review the specific register paths in the Estimated Delay Added for Hold Timing report to determine whether the Fitter adds excessive wire to meet hold timing.
An example of an incorrect constraint which can cause the router to add wire for hold requirements is when there is data transfer from 1x to 2x clocks. Assume the design intent is to allow two cycles per transfer. Data can arrive any time in the two destination clock cycles by adding a multicycle setup constraint as shown in the example:
set_multicycle_path -from 1x -to 2x -setup -end 2
The timing requirement is relaxed by one 2x clock cycle, as shown in the black line in the waveform in the figure.
set_multicycle_path -from 1x -to 2x -setup -end 2 set_multicycle_path -from 1x -to 2x -hold -end 1
The orange dashed line in the figure above represents the hold relationship, and no extra wire is required to delay the data.
The router can also add wire for hold timing requirements when data transfers in the same clock domain, but between clock branches that use different buffering. Transferring between clock network types happens more often between the periphery and the core. The following figure shows data is coming into a device, a periphery clock drives the source register, and a global clock drives the destination register. A global clock buffer has larger insertion delay than a periphery clock buffer. The clock delay to the destination register is much larger than to the source register, hence extra delay is necessary on the data path to ensure that it meets its hold requirement.
To identify cases where a path has different clock network types, review the path in the Timing Analyzer, and check nodes along the source and destination clock paths. Also, check the source and destination clock frequencies to see whether they are the same, or multiples, and whether there are multicycle exceptions on the paths. Finally, ensure that all cross-domain paths that are false by intent have an associated false path exception.
If you suspect that routing is added to fix real hold problems, you can disable the Optimize hold timing advanced Fitter setting (Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Optimize hold timing). Recompile the design with Optimize hold timing disabled, and then rerun timing analysis to identify and correct any paths that fail hold time requirements.
Evaluate Other Reports and Adjust Settings Accordingly
Difficulty Packing Design
As the effort level of Difficulty Packing Design increases, timing closure gets harder. Going from medium to high can result in significant drop in performance or increase in compile time. Consider reducing logic to reduce packing difficulty.
Review Ignored Assignments
Review Non-Default Settings
Review Floorplan
For example, logic that interfaces with I/Os should be close to the I/Os, and logic that interfaces with an IP or memory should be close to the IP or memory.
The following notes describe how you can use the visualization in Floorplan with Color-Coded Entities to check timing paths:
- The green block is spread apart. Check to see if those paths are failing timing, and if so, what connects to that module that could affect placement.
- The blue and aqua blocks are spread out and mixed together. Check if connections between the two modules contribute to this.
- The pink logic at the bottom must interface with I/Os at the bottom
edge. Check fan-in and fan-out of a highlighted module by using the buttons on the
task bar.
Look for signals that go a long way across the chip and see if they are contributing to timing failures.
- Check global signal usage for signals that affect logic placement, and verify if the Fitter placed logic feeding a global buffer close to the buffer and away from related logic. Use settings like high fan-out on non-global resource to pull logic together.
- Check for routing congestion. The Fitter spreads out logic in highly congested areas, making the design harder to route.
Evaluate Placement and Routing
Adjust Placement Effort
Adjust the multiplier after reviewing and optimizing other settings and RTL. Try an increased value, up to 4, and reset to default if performance or compile time does not improve.
Adjust Fitter Effort
By default, the Fitter Optimization mode is set to Balanced (Normal flow) mode, which reduces Fitter effort and compilation time as soon as timing requirements are met. You can optionally select another Optimization mode to target performance, area, routability, power, or compile time.
To increase Fitter effort further, you can also enable the Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Fitter Effort option. The default Auto Fit setting reduces Fitter effort once timing requirements are met. Standard Fit (highest effort) setting uses maximum effort regardless of the design's requirements, leading to higher compilation time and more timing margin.
Review Timing Constraints
Evaluate Clustering Difficulty
- If your design is full but clustering difficulty is low or medium, your design itself, rather than clustering, is likely the main cause of congestion.
- Conversely, congestion occurring after adding a small amount of logic to the design, can be due to clustering. If clustering difficulty is high, this contributes to congestion regardless of design size.
Review Details of Timing Paths
Show Timing Path Routing
In the Timing Analyzer Report Timing dialog box, enable the Report panel name and Show routing options, and click Report Timing.
The Extra Fitter Information tab shows a miniature floorplan with the path highlighted. The Extra Fitter Information tab is not available for Intel® Stratix® 10 devices.
You can also locate the path in the Chip Planner to examine routing congestion, and to view whether nodes in a path are placed close together or far apart.
Global Network Buffers
- CLK_CTRL_Gn—for Global driver
- CLk_CTRL_Rn—for Regional driver
Buffers to access the global networks are located in the center of each side of the device. Buffering to route a core logic signal on a global signal network causes insertion delay. Tradeoffs to consider for global and non-global routing are source location, insertion delay, fan-out, distance a signal travels, and possible congestion if the signal is demoted to local routing.
Source Location
Insertion Delay
set_multicycle_path -from <generating_register> -setup -end 2
Fan-Out
Global Networks
Resets and Global Networks
Suspicious Setup
One typical cause is math precision error. For example, 10Mhz/3 = 33.33 ns per period. In three cycles, the time is 99.999 ns vs 100.000 ns. Setting a maximum delay can provide an appropriate setup relationship.
Another cause of failure are paths that must be false by design intent, such as:
- Asynchronous paths handled through FIFOs, or
- Slow asynchronous paths that rely on handshaking for data that remain available for multiple clock cycles.
To prevent the Fitter from having to meet unnecessarily restrictive timing requirements, consider adding false or multicycle path statements.
Logic Depth
Auto Shift Register Replacement
- If paths that fail timing begin or end in shift registers, consider disabling the Auto Shift Register Replacement option. Do not convert registers that are intended for pipelining.
- For shift registers that are converted to a chain, evaluate area/speed trade off of implementing in RAM or logic cells.
- If a design is close to full, you can save area by shifting register conversion to RAM, benefiting non-critical clock domains. You can change the settings from the default AUTO to OFF globally, or on a register or hierarchy basis.
Clocking Architecture
Timing failure can occur when the I/O interface at the top of the device connects to logic driven by a regional clock which is in one quadrant of the device, and placement restrictions force long paths to and from I/Os to logic across quadrants.
Use a different type of clock source to drive the logic - global, which covers the whole device, or dual-regional which covers half the device. Alternatively, you can reduce the frequency of the I/O interface to accommodate the long path delays. You can also redesign the pinout of the device to place all the specified I/Os adjacent to the regional clock quadrant. This issue can happen when register locations are restricted, such as with Logic Lock regions, clocking resources, or hard blocks (memories, DSPs, IPs).
The Extra Fitter Information tab in the Timing Analyzer timing report informs you when placement is restricted for nodes in a path. The Extra Fitter Information tab is not available for Intel® Stratix® 10 devices.
Timing Closure Recommendations
Adjusting and Recompiling
To reach timing closure, a well written RTL can be more effective than changing your compilation settings. Seed sweeping can also be useful if the timing failure is very small, and the design has already been optimized for performance improvements and is close to final release. Additionally, seed sweeping can be used for evaluating changes to compilation settings. Compilation results vary due to the random nature of fitter algorithms. If a compilation setting change produces lower average performance, undo the change.
Sometimes, settings or constraints can cause more problems than they fix. When significant changes to the RTL or design architecture have been made, compile periodically with default settings and without Logic Lock regions, and re-evaluate paths that fail timing.
Partitioning often does not help timing closure, and must be done at the beginning of the design process. Adding partitions can increase logic utilization if it prevents cross-boundary optimizations, making timing closure harder and increasing compile times.
Using Partitions to Achieve Timing Closure
One technique to achieve timing closure is confining failing paths within individual design partitions, such that there are no failing paths passing between partitions. You can then use incremental make changes as necessary to correct the failing paths, and recompile only the affected partitions.
To use this technique:
-
In the Design Partition Planner, load timing data by clicking
View > Show Timing Data.
Entities containing nodes on failing paths appear in red in the Design Partition Planner.
-
Extract the entity containing failing paths by dragging it
outside of the top-level entity window.
- If there are no failing paths between the extracted entity and the top-level entity, right-click the extracted entity, and then click Create Design Partition to place that entity in its own partition.
-
Keep failing paths within a partition, so that there are no
failing paths crossing between partitions.
If you are unable to isolate the failing paths from an extracted entity so that none are crossing partition boundaries, return the entity to its parent without creating a partition.
-
Find the partition having the worst slack value. For all the
other partitions, preserve the contents and set as
Empty.
For information about preserving the contents of a partition, refer to Incremental Block-Based Compilation Flow in the Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design .
- Adjust the logic in the partition and rerun the Fitter as necessary until the partition meets the timing requirements.
- Repeat the process for all other design partitions with failing paths.
Design Analysis
Ignored Timing Constraints
You can view a list of ignored constraints in the Timing Analyzer GUI by clicking Reports > Report Ignored Constraints or by typing the following command to generate a list of ignored timing constraints:
report_sdc -ignored -panel_name "Ignored Constraints"
Analyze any constraints that the Intel® Quartus® Prime software ignores. If necessary, correct the constraints and recompile your design before proceeding with design optimization.
You can view a list of ignored assignment in the Ignored Assignment Report generated by the Fitter.
I/O Timing
The I/O paths that do not meet the required timing performance are reported as having negative slack and are highlighted in red in the Timing Analyzer Report pane. In cases where you do not apply an explicit I/O timing constraint to an I/O pin, the Intel® Quartus® Prime timing analysis software still reports the Actual number, which is the timing number that must be met for that timing parameter when the device runs in your system.
Register-to-Register Timing Analysis
Displaying Path Reports with the Timing Analyzer
If any clock domains have failing paths (highlighted in red in the Report pane), right-click the clock name listed in the Clocks Summary pane and select Report Timing to get more details.
When you select a path in the Summary of Paths tab, the path detail pane displays all the path information. The Extra Fitter Information tab offers visual representation of the path location on the physical device. This can reveal whether the timing failure is distance related, due to the source and destination node being too close or too far. The Extra Fitter Information tab is not available for Intel® Stratix® 10 devices.
The Data Path tab displays the Data Arrival Path and the Data Required Path. You can determine the path segments contributing the most to the timing violations with the incremental information. The Waveform tab shows the signals in the time domain, and plots the slack between arrival data and required data.
The Technology Map Viewer provides schematic, technology-mapped, representations of the design netlist, and can help you to assess which areas in a design can benefit from reducing the number of logic levels. To locate a timing path in one of the viewers, right-click a path in the timing report, point to Locate Path, and select Locate in Technology Map Viewer. You can also investigate the physical layout of a path in detail with the Chip Planner.
Tips for Analyzing Failing Paths
- Focus on improving the paths that show the worst slack. The Fitter works hardest on paths with the worst slack. If you fix these paths, the Fitter might be able to improve the other failing timing paths in the design.
- Check for nodes that appear in many failing paths. These nodes are at the top of the list in a timing report panel, along with their minimum slacks. Look for paths that have common source registers, destination registers, or common intermediate combinational nodes. In some cases, the registers are not identical, but are part of the same bus.
- In the timing analysis report panels, click the From or To column headings to sort the paths by source or destination registers. If you see common nodes, these nodes indicate areas of your design that might be improved through source code changes or Intel® Quartus® Prime optimization settings. Constraining the placement for just one of the paths might decrease the timing performance for other paths by moving the common node further away in the device.
Tips for Analyzing Failing Clock Paths that Cross Clock Domains
-
Check whether these paths cross two clock domains.
In paths that cross two clock domains, the From Clock and To Clock in the timing analysis report are different.Figure 27. Different Value in From Clock and To Clock Field
- Check if the design contains paths that involve a different clock in the middle of the path, even if the source and destination register clock are the same.
-
Check whether failing paths between these clock domains need to
be analyzed synchronously.
Set failing paths that are not to be analyzed synchronously as false paths.
-
When you run report_timing on a design, the report shows the launch clock and latch clock for each failing path. Check whether the relationship between the launch clock and latch clock is realistic and what you expect from your knowledge of the design
For example, the path can start at a rising edge and end at a falling edge, which reduces the setup relationship by one half clock cycle.
-
Review the clock skew that appears in the Timing Report:
A large skew may indicate a problem in the design, such as a gated clock, or a problem in the physical layout (for example, a clock using local routing instead of dedicated clock routing). When you have made sure the paths are analyzed synchronously and that there is no large skew on the path, and that the constraints are correct, you can analyze the data path. These steps help you fine tune your constraints for paths across clock domains to ensure you get an accurate timing report.
-
Check if the PLL phase shift is reducing the setup
requirement.
You might adjust this by using PLL parameters and settings.
- Ignore paths that cross clock domains for logic protected with synchronization logic (for example, FIFOs or double-data synchronization registers), even if the clocks are related.
-
Set false path constraints on all unnecessary paths:
Attempting to optimize unnecessary paths can prevent the Fitter from meeting the timing requirements on timing paths that are critical to the design.
Tips for Analyzing Paths from/to the Source and Destination of Critical Path
To understand what may be pulling on a critical path, the following report_timing command can be useful.
- In the project directory, run the report_timing command to find the nodes in a critical path.
-
Copy the code below in a .tcl file, and replace the first two
variable with the node names from the From Node and To Node columns of the
worst path. The script analyzes the path between the worst source and
destination registers.
set wrst_src <insert_source_of_worst_path_here> set wrst_dst <insert_destination_of_worst_path_here> report_timing -setup -npaths 50 -detail path_only -from $wrst_src \ -panel_name "Worst Path||wrst_src -> *" report_timing -setup -npaths 50 -detail path_only -to $wrst_dst \ -panel_name "Worst Path||* -> wrst_dst" report_timing -setup -npaths 50 -detail path_only -to $wrst_src \ -panel_name "Worst Path||* -> wrst_src" report_timing -setup -npaths 50 -detail path_only -from $wrst_dst \ -panel_name "Worst Path||wrst_dst -> *"
- From the Script menu, source the .tcl file.
-
In the resulting timing panel, locate timing failed paths
(highlighted in red) in the Chip Planner, and view information such as distance
between the nodes and large fanouts.
The figure shows a simplified example of what these reports analyzed.
Figure 28. Timing ReportThe critical path of the design is in red. The relation between the .tcl script and the figure is:
- The first two lines show everything inside the two endpoints of the critical path that
are pulling them in different directions.
- The first report_timing command analyzes all paths the source is driving, shown in green.
- The second report_timing command analyzes all paths going to the destination, including the critical path, shown in orange.
- The last two report_timing commands show everything outside of the endpoints pulling them in other directions.
- The first two lines show everything inside the two endpoints of the critical path that
are pulling them in different directions.
Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles
This behavior happens in high speed designs where many register-to-register paths have very little slack. Different placements can then result in timing failures in the marginal paths.
- In the project directory, create a script named TQ_critical_paths.tcl.
-
After compilation, review the critical paths and then write a generic report_timing command to capture those
paths.
For example, if several paths fail in a low-level hierarchy, add a command such as:
report_timing –setup –npaths 50 –detail path_only \ –to “main_system: main_system_inst|app_cpu:cpu|*” \ –panel_name “Critical Paths||s: * -> app_cpu”
-
If there is a specific path, such as a bit of a state-machine going to other *count_sync* registers, you can add a
command similar to:
report_timing –setup –npaths 50 –detail path_only \ –from “main_system: main_system_inst|egress_count_sm:egress_inst|update” \ –to “*count_sync*” –panel_name “Critical Paths||s: egress_sm|update -> count_sync”
-
Execute this script in the Timing Analyzer after every compilation,
and add new report_timing
commands as new critical paths appear.
This helps you monitor paths that consistently fail and paths that are only marginal, so you can prioritize effectively
Global Routing Resources
For details about the number and types of global routing resources available, refer to the relevant device handbook.
Check the global signal utilization in your design to ensure that the appropriate signals have been placed on the global routing resources. In the Compilation Report, open the Fitter report and click Resource Section. Analyze the Global & Other Fast Signals and Non-Global High Fan-out Signals reports to determine whether any changes are required.
You might be able to reduce skew for high fan-out signals by placing them on global routing resources. Conversely, you can reduce the insertion delay of low fan-out signals by removing them from global routing resources. Doing so can improve clock enable timing and control signal recovery/removal timing, but increases clock skew. Use the Global Signal setting in the Assignment Editor to control global routing resources.
Timing Optimization
Displaying Timing Closure Recommendations for Failing Paths
- In the Tasks pane of the Timing Analyzer, select the Report Timing Closure Recommendations task to open the Report Timing Closure Recommendations dialog box.
- Select paths based on the clock domain, filter by nodes on path, and choose the number of paths to analyze.
- After running the Report Timing Closure Recommendations task in the Timing Analyzer, examine the reports in the Report Timing Closure Recommendations folder in the Report pane of the Timing Analyzer GUI. Each recommendation has star symbols (*) associated with it. Recommendations with more stars are more likely to help you close timing on your design.
The reports give you the most probable causes of failure for each analyzed path, and show recommendations that may help you fix the failing paths.
The reports are organized into sections, depending on the type of issues found in the design, such as large clock skew, restricted optimizations, unbalanced logic, skipped optimizations, coding style that has too many levels of logic between registers, or region or partition constraints specific to your project.
For detailed analysis of the critical paths, run the report_timing command on specified paths. In the Extra Fitter Information tab of the Path report panel, you can see detailed fitter-related information that may help you visualize the issue. The Extra Fitter Information tab is not available for Intel® Stratix® 10 devices.
Timing Optimization Advisor
The Timing Optimization Advisor guides you in making settings that optimize your design to meet your timing requirements. To run the Timing Optimization Advisor click Tools > Advisors > Timing Optimization Advisor. This advisor describes many of the suggestions made in this section.
When you open the Timing Optimization Advisor after compilation, you can find recommendations to improve the timing performance of your design. If suggestions in these advisors contradict each other, evaluate these options and choose the settings that best suit the given requirements.
The example shows the Timing Optimization Advisor after compiling a design that meets its frequency requirements, but requires setting changes to improve the timing.
When you expand one of the categories in the Timing Optimization Advisor, such as Maximum Frequency (fmax) or I/O Timing (tsu, tco, tpd), the recommendations appear in stages. These stages show the order in which to apply the recommended settings.
The first stage contains the options that are easiest to change, make the least drastic changes to your design optimization, and have the least effect on compilation time.
Icons indicate whether each recommended setting has been made in the current project. In the figure, the checkmark icons in the list of recommendations for Stage 1 indicates recommendations that are already implemented. The warning icons indicate recommendations that are not followed for this compilation. The information icons indicate general suggestions. For these entries, the advisor does not report whether these recommendations were followed, but instead explains how you can achieve better performance. For a legend that provides more information for each icon, refer to the “How to use” page in the Timing Optimization Advisor.
Each recommendation provides a link to the appropriate location in the Intel® Quartus® Prime GUI where you can change the settings. For example, consider the Synthesis Netlist Optimizations page of the Settings dialog box or the Global Signals category in the Assignment Editor. This approach provides the most control over which settings are made and helps you learn about the settings in the software. When available, you can also use the Correct the Settings button to automatically make the suggested change to global settings.
For some entries in the Timing Optimization Advisor, a button allows you to further analyze your design and see more information. The advisor provides a table with the clocks in the design, indicating whether they have been assigned a timing constraint.
Optional Fitter Settings
Optimize Hold Timing
When you turn on Optimize Hold Timing in the Advanced Fitter Settings dialog box, the Intel® Quartus® Prime software adds delay to paths to ensure that your design meets the minimum delay requirements. If you select I/O Paths and Minimum TPD Paths, the Fitter works to meet the following criteria:
- Hold times (tH) from the device input pins to the registers
- Minimum delays from I/O pins to I/O registers or from I/O registers to I/O pins
- Minimum clock-to-out time (tCO) from registers to output pins
If you select All Paths, the Fitter also works to meet hold requirements from registers to registers, as highlighted in blue in the figure, in which a derived clock generated with logic causes a hold time problem on another register.
However, if your design still has internal hold time violations between registers, you can manually add delays by instantiating LCELL primitives, or by making changes to your design, such as using a clock enable signal instead of a derived or gated clock.
Fitter Aggressive Routability Optimization
This option is useful if routing resources are resulting in no-fit errors, and you want to reduce routing wire use.
The table lists the settings for the Fitter Aggressive Routability Optimizations logic option.
Settings | Description |
---|---|
Always | The Fitter always performs aggressive routability optimizations. If you set the Fitter Aggressive Routability Optimizations logic option to Always, reducing wire utilization may affect the performance of your design. |
Never | The Fitter never performs aggressive routability optimizations. If improving timing is more important than reducing wire usage, then set this option to Automatically or Never. |
Automatically | The Fitter performs aggressive routability optimizations automatically, based on the routability and timing requirements of the design. If improving timing is more important than reducing wire usage, then set this option to Automatically or Never. |
I/O Timing Optimization Techniques
This stage of design optimization focuses on I/O timing, including setup delay (tSU), hold time (tH), and clock-to-output (tCO) parameters.
- The design's assignments follow the suggestions in the Initial Compilation: Required Settings section of the Design Optimization Overview chapter.
- Resource utilization is satisfactory.
Summary of Techniques for Improving Setup and Clock-to-Output Times
The table lists the recommended order of techniques to reduce tSU and tCO times. Reducing tSU times increases hold (tH) times.
Order | Technique | Affects tSU | Affects tCO |
---|---|---|---|
1 | Verify of that the appropriate constraints are set for the failing I/Os (refer to Initial Compilation: Required Settings) | Yes | Yes |
2 | Use timing-driven compilation for I/O (refer to Fast Input, Output, and Output Enable Registers) | Yes | Yes |
3 | Use fast input register (refer to Programmable Delays) | Yes | N/A |
4 | Use fast output register, fast output enable register, and fast OCT register (refer to Programmable Delays) | N/A | Yes |
5 | Decrease the value of Input Delay from Pin to Input Register or set Decrease Input Delay to Input Register = ON | Yes | N/A |
6 | Decrease the value of Input Delay from Pin to Internal Cells or set Decrease Input Delay to Internal Cells = ON | Yes | N/A |
7 | Decrease the value of Delay from Output Register to Output Pin or set Increase Delay to Output Pin = OFF (refer to Fast Input, Output, and Output Enable Registers) | N/A | Yes |
8 | Increase the value of Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations (refer to Fast Input, Output, and Output Enable Registers) | Yes | N/A |
9 | Use PLLs to shift clock edges | Yes | Yes |
10 | Increase the value of Delay to output enable pin or set Increase delay to output enable pin (refer to Use PLLs to Shift Clock Edges) | N/A | Yes |
- Optimize IOC Register Placement for Timing Logic Option
This option moves registers into I/O elements to meet tSU or tCO assignments, duplicating the register if necessary (as in the case in which a register fans out to multiple output locations). - Fast Input, Output, and Output Enable Registers
You can place individual registers in I/O cells manually by making fast I/O assignments with the Assignment Editor. - Programmable Delays
You can use various programmable delay options to minimize the tSU and tCO times. - Use PLLs to Shift Clock Edges
Using a PLL typically improves I/O timing automatically. - Use Fast Regional Clock Networks and Regional Clocks Networks
Regional clocks provide the lowest clock delay and skew for logic contained in a single quadrant. - Spine Clock Limitations
In projects with high clock routing demands, limitations in the Intel® Quartus® Prime software can cause spine clock errors.
Optimize IOC Register Placement for Timing Logic Option
- Have combinational logic between the register and the pin
- Are part of a carry chain
- Have an overriding location assignment
- Use the asynchronous load port and the value is not 1 (in device families where the port is available)
Fast Input, Output, and Output Enable Registers
If the fast I/O setting is on, the register is always placed in the I/O element. If the fast I/O setting is off, the register is never placed in the I/O element. This is true even if the Optimize IOC Register Placement for Timing option is turned on. If there is no fast I/O assignment, the Intel® Quartus® Prime software determines whether to place registers in I/O elements if the Optimize IOC Register Placement for Timing option is turned on.
You can also use the four fast I/O options (Fast Input Register, Fast Output Register, Fast Output Enable Register, and Fast OCT Register) to override the location of a register that is in a Logic Lock region and force it into an I/O cell. If you apply this assignment to a register that feeds multiple pins, the Fitter duplicates the register and places it in all relevant I/O elements.
For more information about the Fast Input Register option, Fast Output Register option, Fast Output Enable Register option, and Fast OCT (on-chip termination) Register option, refer to Intel® Quartus® Prime Help.
Programmable Delays
The Intel® Quartus® Prime software automatically adjusts the applicable programmable delays to help meet timing requirements. For detailed information about the effect of these options, refer to the device family handbook or data sheet.
After you have made a programmable delay assignment and compiled the design, you can view the implemented delay values for every delay chain and every I/O pin in the Delay Chain Summary section of the Compilation Report.
You can assign programmable delay options to supported nodes with the Assignment Editor. You can also view and modify the delay chain setting for the target device with the Chip Planner and Resource Property Editor. When you use the Resource Property Editor to make changes after performing a full compilation, recompiling the entire design is not necessary; you can save changes directly to the netlist. Because these changes are made directly to the netlist, the changes are not made again automatically when you recompile the design. The change management features allow you to reapply the changes on subsequent compilations.
Although the programmable delays in newer devices are user-controllable, Intel recommends their use for advanced users only. However, the Intel® Quartus® Prime software might use the programmable delays internally during the Fitter phase.
For details about the programmable delay logic options available for Intel devices, refer to the following Intel® Quartus® Prime Help topics:
Use PLLs to Shift Clock Edges
You can achieve the same type of effect in certain devices by using the programmable delay called Input Delay from Dual Purpose Clock Pin to Fan-Out Destinations.
Use Fast Regional Clock Networks and Regional Clocks Networks
Intel devices have a variety of hierarchical clock structures. These include dedicated global clock networks, regional clock networks, fast regional clock networks, and periphery clock networks. The available resources differ between the various Intel device families.
For the number of clocking resources available in your target device, refer to the appropriate device handbook.
Spine Clock Limitations
Global clock networks, regional clock networks, and periphery clock networks have an additional level of clock hierarchy known as spine clocks. Spine clocks drive the final row and column clocks to their registers; thus, the clock to every register in the chip is reached through spine clocks. Spine clocks are not directly user controllable.
To reduce these spine clock errors, constrain your design to use your regional clock resources better:
- If your design does not use Logic Lock regions, or if the Logic Lock regions are not aligned to your clock region boundaries, create additional Logic Lock regions and further constrain your logic.
- If Periphery features ignore Logic Lock region assignment, possibly because the global promotion process is not functioning properly. To ensure that the global promotion process uses the correct locations, assign specific pins to the I/Os using these periphery features.
- By default, some Intel® FPGA IP functions apply a global signal assignment with a value of dual-regional clock. If you constrain your logic to a regional clock region and set the global signal assignment to Regional instead of Dual-Regional, you can reduce clock resource contention.
Register-to-Register Timing Optimization Techniques
Coding style affects the performance of a design to a greater extent than other changes in settings. Always evaluate the code and make sure to use synchronous design practices.
Before performing design optimizations, understand the structure of the design as well as the effects of techniques in different types of logic. Techniques that do not benefit the logic structure can decrease performance.
Optimize Source Code
Be aware of the number of logic levels needed to implement your logic while you are coding. Too many levels of logic between registers might result in critical paths failing timing. Try restructuring the design to use pipelining or more efficient coding techniques. Also, try limiting high fan-out signals in the source code. When possible, duplicate and pipeline control signals. Make sure the duplicate registers are protected by a preserve attribute, to avoid merging during synthesis.
If the critical path in your design involves memory or DSP functions, check whether you have code blocks in your design that describe memory or functions that are not being inferred and placed in dedicated logic. You might be able to modify your source code to cause these functions to be placed into high-performance dedicated memory or resources in the target device. When using RAM/DSP blocks, enable the optional input and output registers.
Ensure that your state machines are recognized as state machine logic and optimized appropriately in your synthesis tool. State machines that are recognized are generally optimized better than if the synthesis tool treats them as generic logic. In the Intel® Quartus® Prime software, you can check the State Machine report under Analysis & Synthesis in the Compilation Report. This report provides details, including state encoding for each state machine that was recognized during compilation. If your state machine is not recognized, you might have to change your source code to enable it to be recognized.
Improving Register-to-Register Timing
- Ensure that your timing assignments are complete and correct. For details, refer to the Initial Compilation: Required Settings section in the Design Optimization Overview chapter.
- Review all warning messages from your initial compilation and check for ignored timing assignments.
- Apply netlist synthesis optimization options.
-
To optimize for speed, apply the
following synthesis options:
- Optimize Synthesis for Speed, Not Area
- Flatten the Hierarchy During Synthesis
- Set the Synthesis Effort to High
- Prevent Shift Register Inference
- Use Other Synthesis Options Available in Your Synthesis Tool
- To optimize for performance, turn on Advanced Physical Optimization
-
Try different Fitter seeds. If only a
small number of paths are failing by small negative slack, then you can try with
a different seed to find a fit that meets constraints in the Fitter seed
noise.
Note: Omit this step if a large number of critical paths are failing, or if the paths are failing by a long margin.
- To control placement, make Logic Lock assignments.
- Modify your design source code to fix areas of the design that are still failing timing requirements by significant amounts.
-
Make location assignments, or as a
last resort, perform manual placement by back-annotating the design.
You can use Design Space Explorer II (DSE) to automate the process of running different compilations with different settings.If these techniques do not achieve performance requirements, additional design source code modifications might be required.
Physical Synthesis Optimizations
During the synthesis stage of the Intel® Quartus® Prime compilation, physical synthesis optimizations operate either on the output from another EDA synthesis tool, or as an intermediate step in synthesis. These optimizations modify the synthesis netlist to improve either area or speed, depending on the technique and effort level you select.
To view and modify the synthesis netlist optimization options, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter).
If you use a third-party EDA synthesis tool and want to determine if the Intel® Quartus® Prime software can remap the circuit to improve performance, use the Perform WYSIWYG Primitive Resynthesis option. This option directs the Intel® Quartus® Prime software to un-map the LEs in an atom netlist to logic gates, and then map the gates back to Intel-specific primitives. Intel-specific primitives enable the Fitter to remap the circuits using architecture-specific techniques.
The Intel® Quartus® Prime technology mapper optimizes the design to achieve maximum speed performance, minimum area usage, or balances high performance and minimal logic usage, according to the setting of the Optimization Technique option. Set this option to Speed or Balanced.
During the Fitter stage of the Intel® Quartus® Prime compilation, physical synthesis optimizations make placement-specific changes to the netlist that improve speed performance results for the specific Intel device.
Turn Off Extra-Effort Power Optimization Settings
Optimize Synthesis for Speed, Not Area
Identify the default optimization targets of your Synthesis tool, and set your device and timing constraints accordingly. For example, if you do not specify a target frequency, some synthesis tools optimize for area.
You can specify logic options for specific modules in your design with the Assignment Editor while leaving the default Optimization Technique setting at Balanced (for the best trade-off between area and speed for certain device families) or Area (if area is an important concern). You can also use the Speed Optimization Technique for Clock Domains option in the Assignment Editor to specify that all combinational logic in or between the specified clock domains are optimized for speed.
To achieve best performance with push-button compilation, follow the recommendations in the following sections for other synthesis settings. You can use DSE II to experiment with different Intel® Quartus® Prime synthesis options to optimize your design for the best performance.
Flatten the Hierarchy During Synthesis
Set the Synthesis Effort to High
Duplicate Logic for Fan-Out Control
Synthesis tools support options or attributes that specify the maximum fan-out of a register. When using Intel® Quartus® Prime synthesis, you can set the Maximum Fan-Out logic option in the Assignment Editor to control the number of destinations for a node so that the fan-out count does not exceed a specified value. You can also use the maxfan attribute in your HDL code. The software duplicates the node as required to achieve the specified maximum fan-out.
Logic duplication using Maximum Fan-Out assignments normally increases resource utilization, and can potentially increase compilation time, depending on the placement and the total resource usage within the selected device.
The improvement in timing performance that results from Maximum Fan-Out assignments is design-specific. This is because when you use the Maximum Fan-Out assignment, the Fitter duplicates the source logic to limit the fan-out, but does not to control the destinations that each of the duplicated sources drive. Therefore, it is possible for duplicated source logic to be driving logic located all around the device. To avoid this situation, you can use the Manual Logic Duplication logic option.
If you are using Maximum Fan-Out assignments, benchmark your design with and without these assignments to evaluate whether they give the expected improvement in timing performance. Use the assignments only when you get improved results.
You can manually duplicate registers in the Intel® Quartus® Prime software regardless of the synthesis tool used. To duplicate a register, apply the Manual Logic Duplication logic option to the register with the Assignment Editor.
Prevent Shift Register Inference
Use Other Synthesis Options Available in Your Synthesis Tool
- Turn on register balancing or retiming
- Turn on register pipelining
- Turn off resource sharing
These options can increase performance, but typically increase the resource utilization of your design.
Fitter Seed
Changes in the design impact performance between compilations. This random variation is inherent in placement and routing algorithms—it is impossible to try all seeds and get the absolute best result.
If a change in optimization settings marginally affects the register-to-register timing or number of failing paths, you cannot always be certain that your change caused the improvement or degradation, or whether it is due to random effects in the Fitter. If your design is still changing, running a seed sweep (compiling your design with multiple seeds) determines whether the average result improved after an optimization change, and whether a setting that increases compilation time has benefits worth the increased time, such as with physical synthesis settings. The sweep also shows the amount of random variation to expect for your design.
If your design is finalized you can compile your design with different seeds to obtain one optimal result. However, if you subsequently make any changes to your design, you might need to perform seed sweep again.
Click Assignments > Compiler Settings to control the initial placement with the seed. You can use the DSE II to perform a seed sweep easily.
To specify a Fitter seed use the following Tcl command :
set_global_assignment -name SEED <value>
Set Maximum Router Timing Optimization Level
Location Assignments
Location assignments are less flexible for the Intel® Quartus® Prime Fitter than Logic Lock assignments. Additionally, if you are familiar with your design, you can enter location constraints in a way that produces better results.
Metastability Analysis and Optimization Techniques
You can use the Intel® Quartus® Prime software to analyze the average MTBF due to metastability when a design synchronizes asynchronous signals and to optimize the design to improve the MTBF. These metastability features are supported only for designs constrained with the Timing Analyzer, and for select device families.
If the MTBF of your design is low, refer to the Metastability Optimization section in the Timing Optimization Advisor, which suggests various settings that can help optimize your design in terms of metastability.
This chapter describes how to enable metastability analysis and identify the register synchronization chains in your design, provides details about metastability reports, and provides additional guidelines for managing metastability.
Intel Stratix 10 Timing Closure Recommendations
In traditional FPGA timing closure flows, the starting point for most design analysis is the critical path. Due to the nature of Intel® Stratix® 10 devices and the availability of the Hyper Retimer, it is best to start you timing closure activities from the Retiming Limit Report. You want to give the tool as many optimization opportunities as possible before having to look into more time intensive and potentially manual timing closure techniques.
Retiming Limit Details Report
The Retiming Limit Details report specifies:
- Clock Transfer: Clock domain, or the clock domain transfer for which the critical chain applies
- Limiting Reason: Design conditions which prevent further optimizations from happening.
- Critical Chain Details: Timing paths associated with the timing restrictions.
Using the Retiming Limit Details Report
To access the Retiming Limit Details report:
- In the Reports tab, double-click Retiming Limit Details under Fitter > Retime Stage.
-
To locate the critical chain in the Technology Map Viewer,
right-click any path and click Locate Critical Chain
in Technology Map Viewer.
The Technology Map Viewer displays a schematic representation of the complete critical chain after place, route and register retiming.
Figure 32. Critical Chain in Technology Map Viewer
Fast Forward Timing Closure Recommendations
When running Fast Forward compilation, the Compiler removes signals from registers to allow mobility within the netlist for subsequent retiming. Fast Forward compilation generates design-specific timing closure recommendations, and predicts maximum performance with removal of all timing restrictions.
After you complete Fast Forward explorations, you can determine which recommendations to implement to provide the most benefit. Implement appropriate recommendations in your RTL, and recompile the design to achieve the performance levels that Fast Forward reports.
The Fast Forward Details Report provides the following information:
Name | Description |
---|---|
Step | Displays the various Fast Forward optimization steps, starting
from the pre-optimization base compilation.
|
Fast Forward Optimization | Analyzed Summary of the optimizations necessary to implement each step. |
Estimated fMAX | Estimated fMAX performance after you implement the recommendations for this step in your design. This is cumulative, and step n represents the potential fMAX after implementing all previous steps. |
Optimization Analyzed | (cumulative) List of all the consecutive optimization steps applied. |
Recommendation for Critical Chain | Lists recommended changes to your designs. These recommendations are geared towards removing retiming limitations, and allowing register movement. |
Generating Fast Forward Timing Closure Recommendations
To generate Fast Forward timing closure recommendations:
-
On the Compilation Dashboard, click Fast Forward Timing Closure Recommendations.
The Compiler runs prerequisite synthesis or Fitter stages as needed, and generates timing closure recommendations in the Compilation Report.
- View timing closure recommendations in the Compilation Report to evaluate design performance, and implement key RTL performance improvements.
- To run Fast Forward compilation during each full compilation, click Assignments > Settings > Compiler Settings > HyperFlex, and turn on Run Fast Forward Timing Closure Recommendations during compilation.
- To modify how Fast Forward compilation interprets specific I/O and block types, click Assignments > Settings > Compiler Settings > HyperFlex Advanced Settings.
Implementing Fast Forward Recommendations
After implementing timing closure recommendations in your design, you can rerun the Retime stage to obtain the predictive performance gains.
You can continue exploring performance and implementing RTL changes to your code until you reach the desired performance target. Once you have completed all the modifications you want to do, continue your timing closure activities with the traditional techniques explained in this document.
For more information about implementing Fast Forward timing closure recommendations in your design, refer to the Implement Fast Forward Recommendations section of the Intel® Stratix® 10 High-Performance Design Handbook
Periphery to Core Register Placement and Routing Optimization
Transfers between external interfaces (for example, high-speed I/O or serial interfaces) and the FPGA often require routing many connections with tight setup and hold timing requirements. When this option is turned on, the Fitter performs P2C placement and routing decisions before those for core placement and routing. This reserves the necessary resources to ensure that your design achieves its timing requirements and avoids routing congestion for transfers with external interfaces.
This option is available as a global assignment, or can be applied to specific instances within your design.
- Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box
The Periphery to Core Placement and Routing Optimization setting specifies whether the Fitter optimizes targeted placement and routing on direct connections between periphery logic and registers in the FPGA core. - Setting Periphery to Core Optimizations in the Assignment Editor
When you turn on the Periphery to Core Placement and Routing Optimization (P2C/C2P) setting in the Assignment Editor, the Intel® Quartus® Prime software performs periphery to core, or core to periphery optimizations on selected instances in your design. - Viewing Periphery to Core Optimizations in the Fitter Report
The Intel® Quartus® Prime software generates a periphery to core placement and routing optimization summary in the Fitter (Place & Route) report after compilation.
Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box
You can optionally perform periphery to core optimizations by instance with settings in the Assignment Editor.
- In the Intel® Quartus® Prime software, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter).
-
In the Advanced Fitter Settings dialog box, for the
Periphery to Core Placement and Routing
Optimization option, select one of the following options
depending on how you want to direct periphery to core optimizations in your
design:
- Select Auto to direct the software to automatically identify transfers with tight timing windows, place the core registers, and route all connections to or from the periphery.
-
Select On to
direct the software to globally optimize all transfers between the
periphery and core registers, regardless of timing requirements.
Note: Setting this option to On in the Advanced Fitter Settings is not recommended. The intended use for this setting is in the Assignment Editor to force optimization for a targeted set of nodes or instance.
- Select Off to disable periphery to core path optimization in your design.
Setting Periphery to Core Optimizations in the Assignment Editor
You can optionally perform periphery to core optimizations by instance with settings in the Advanced Fitter Settings dialog box.
- In the Intel® Quartus® Prime software, click Assignments > Assignment Editor.
- For the selected path, double-click the Assignment Name column, and then click the Periphery to core register placement and routing optimization option in the drop-down list.
-
In the To column, choose either a periphery node or
core register node on a P2C/C2P path you want to optimize. Leave the
From column empty.
For paths to appear in the Assignments Editor, you must first run Analysis & Synthesis on your design.

Viewing Periphery to Core Optimizations in the Fitter Report
- Compile your Intel® Quartus® Prime project.
- In the Tasks pane, select Compilation.
- Under Fitter (Place & Route), double-click View Report.
- In the Fitter folder, expand the Place Stage folder.
-
Double-click Periphery to Core Transfer Optimization
Summary.
Table 16. Fitter Report - Periphery to Core Transfer Optimization (P2C) Summary From Path To Path Status Node 1 Node 2 Placed and Routed—Core register is locked. Periphery to core/core to periphery routing is committed. Node 3 Node 4 Placed but not Routed—Core register is locked. Routing is not committed. This occurs when P2C is not able to optimize all targeted paths within a single group, for example, the same delay/wire requirement, or the same control signals. Partial P2C routing commitments may cause unresolvable routing congestion. Node 5 Node 6 Not Optimized—This occurs when P2C is set to Auto and the path is not optimized due to one of the following issues: - The delay requirement is impossible to achieve.
- The minimum delay requirement (for hold timing) is too large. The P2C algorithm cannot efficiently handle cases when many wires need to be added to meet hold timing.
- P2C encountered unresolvable routing congestion for this particular path.
Scripting Support
quartus_sh --qhelp
You can specify many of the options described in this section either in an instance, or at a global level, or both.
Use the following Tcl command to make a global assignment:
set_global_assignment -name <.qsf variable name> <value>
Use the following Tcl command to make an instance assignment:
set_instance_assignment -name <.qsf variable name> <value> -to <instance name>
Initial Compilation Settings
The top table lists the .qsf variable name and applicable values for the settings described in the Initial Compilation: Required Settings section in the Design Optimization Overview chapter. The bottom table lists the advanced compilation settings.
Setting Name | .qsf File Variable Name | Values | Type |
---|---|---|---|
Optimize IOC Register Placement For Timing | OPTIMIZE_IOC_REGISTER_ PLACEMENT_FOR_TIMING | ON, OFF | Global |
Optimize Hold Timing | OPTIMIZE_HOLD_TIMING | OFF, IO PATHS AND MINIMUM TPD PATHS, ALL PATHS | Global |
Setting Name | .qsf File Variable Name | Values | Type |
---|---|---|---|
Router Timing Optimization level | ROUTER_TIMING_OPTIMIZATION_LEVEL | NORMAL, MINIMUM, MAXIMUM | Global |
I/O Timing Optimization Techniques
Setting Name | .qsf File Variable Name | Values | Type |
---|---|---|---|
Optimize IOC Register Placement For Timing | OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING | ON, OFF | Global |
Fast Input Register | FAST_INPUT_REGISTER | ON, OFF | Instance |
Fast Output Register | FAST_OUTPUT_REGISTER | ON, OFF | Instance |
Fast Output Enable Register | FAST_OUTPUT_ENABLE_REGISTER | ON, OFF | Instance |
Fast OCT Register | FAST_OCT_REGISTER | ON, OFF | Instance |
Register-to-Register Timing Optimization Techniques
The table lists the .qsf file variable name and applicable values for the settings described in Register-to-Register Timing Optimization Techniques.
Setting Name | .qsf File Variable Name | Values | Type |
---|---|---|---|
Perform WYSIWYG Primitive Resynthesis | ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP | ON, OFF | Global, Instance |
Fitter Seed | SEED | <integer> | Global |
Maximum Fan-Out | MAX_FANOUT | <integer> | Instance |
Manual Logic Duplication | DUPLICATE_ATOM | <node name> | Instance |
Optimize Power during Synthesis | OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL, OFF EXTRA_EFFORT | Global |
Optimize Power during Fitting | OPTIMIZE_POWER_DURING_FITTING | NORMAL, OFF EXTRA_EFFORT | Global |
Timing Closure and Optimization Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.11.12 | 18.1.0 |
|
2018.09.24 | 18.1.0 |
|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.02 | 16.0.0 |
|
2015.11.02 | 15.1.0 |
|
2014.12.15 | 14.1.0 |
|
June 2014 | 14.0.0 |
|
November 2013 | 13.1.0 |
|
May 2013 | 13.0.0 |
|
November 2012 | 12.1.0 |
|
June 2012 | 12.0.0 |
|
November 2011 | 11.1.0 |
|
May 2011 | 11.0.0 |
|
December 2010 | 10.1.0 |
|
August 2010 | 10.0.1 | Corrected link |
July 2010 | 10.0.0 |
|
Analyzing and Optimizing the Design Floorplan
Design floorplan analysis helps to close timing, and ensures optimal performance in highly complex designs. With analysis capability, the Intel® Quartus® Prime Chip Planner helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.
You can perform design analysis, as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.
For information about the Early Place Flow, refer to the Intel® Quartus® Prime Pro Edition User Guide: Compiler .
For information about floorplanning a Partial Reconfiguration design, refer to the Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration .
Design Floorplan Analysis in the Chip Planner
The Chip Planner showcases:
|
|
Starting the Chip Planner
- Click the Chip Planner icon
on the Intel® Quartus® Prime software toolbar.
- In the
following tools, right-click any chip resource and select Locate > Locate in Chip
Planner:
- Compilation Report
- Logic Lock Regions Window
- Technology Map Viewer
- Project Navigator window
- Node Finder
- Simulation Report
- Report Timing panel of the Timing Analyzer
Chip Planner GUI Components
Chip Planner Toolbar
Layers Settings
Layers Settings Pane
With the Layers Settings pane, you can manage the graphic elements that the Chip Planner displays.
You open the Layers Settings pane by clicking View > Layers Settings. The Layers Settings pane offers layer presets, which group resources that are often used together. The Basic, Detailed, and Floorplan Editing default presets are useful for general assignment-related activities. You can also create custom presets tailored to your needs.
Locate History Window
If you locate a required path from the Timing Analyzer Report Timing pane, the Locate History window displays the required clock path. If you locate an arrival path from the Timing Analyzer Report Timing pane, the Locate History window displays the path from the arrival clock to the arrival data. Double-clicking a node or path in the Locate History window displays the selected node or path in the Chip Planner.
Chip Planner Floorplan Views
Bird’s Eye View
The Bird’s Eye View displays a high-level picture of resource usage for the entire chip and provides a fast and efficient way to navigate between areas of interest in the Chip Planner.
The Bird’s Eye View is particularly useful when the parts of your design that you want to view are at opposite ends of the chip, and you want to quickly navigate between resource elements without losing your frame of reference.
Properties Window
The Properties window displays detailed properties of the objects (such as atoms, paths, Logic Lock regions, or routing elements) currently selected in the Chip Planner. To display the Properties window, right-click the object and select View > Properties.
Viewing Architecture-Specific Design Information
- Device routing resources used by your design—View how blocks are connected, as well as the signal routing that connects the blocks.
- LE configuration—View logic element (LE) configuration in your design. For example, you can view which LE inputs are used; whether the LE utilizes the register, the look-up table (LUT), or both; as well as the signal flow through the LE.
- ALM configuration—View ALM configuration in your design. For example, you can view which ALM inputs are used; whether the ALM utilizes the registers, the upper LUT, the lower LUT, or all of them. You can also view the signal flow through the ALM.
- I/O configuration—View device I/O resource usage. For example, you can view which components of the I/O resources are used, whether the delay chain settings are enabled, which I/O standards are set, and the signal flow through the I/O.
- PLL configuration—View phase-locked loop (PLL) configuration in your design. For example, you can view which control signals of the PLL are used with the settings for your PLL.
- Timing—View the delay between the inputs and outputs of FPGA elements. For example, you can analyze the timing of the DATAB input to the COMBOUT output.
Viewing Available Clock Networks in the Device
- Depending on the clock layers that you activate in the Layers Settings pane, the Chip Planner displays regional and global clock regions in the device, and the connectivity between clock regions, pins, and PLLs.
- Clock regions appear as rectangular overlay boxes with labels indicating the clock type and index. Select a clock network region by clicking the clock region. The clock-shaped icon at the top-left corner indicates that the region represents a clock network region.
- Spine/sector clock regions have a dotted vertical line in the middle. This dotted line indicates where two columns of row clocks meet in a sector clock.
- To change the color in which the Chip Planner displays clock regions, select Tools > Options > Colors > Clock Regions.
Viewing Clock Sector Utilization
- In the Tasks pane, double-click Report Clock Sector Utilization to open the Report Clock Sector Utilization dialog box.
-
If you want the report to include the source nodes, turn on Report source nodes.
The equivalent TCL command appears at the bottom of the Dialog Box.
-
Click OK.
The report output shows the most used clock sectors.
The Report pane displays a list of clock sectors, with colors according to utilization. The clock sector with the highest utilization appears in red, and the sector with least utilization appears in blue.
You can turn on or off the sector visibility from the Report pane. You can also highlight nodes, if applicable.
Viewing Routing Congestion
To view the routing congestion in the Chip Planner:
- In the Tasks pane, double-click the Report Routing Utilization command to launch the Report Routing Utilization dialog box.
- Click Preview in the Report Routing Utilization dialog box to preview the default congestion display.
-
Change the Routing Utilization
Type to display congestion for specific resources.
The default display uses dark blue for 0% congestion (blue indicates zero utilization) and red for 100%. You can adjust the slider for Threshold percentage to change the congestion threshold level.
The congestion map helps you determine whether you can modify the floorplan, or modify the RTL to reduce routing congestion. Consider:
- The routing congestion map uses the color and shading of logic resources to indicate relative resource utilization; darker shading represents a greater utilization of routing resources. Areas where routing utilization exceeds the threshold value that you specify in the Report Routing Utilization dialog box appear in red.
- To identify a lack of routing resources, you must investigate each routing interconnect type separately by selecting each interconnect type in turn in the Routing Utilization Settings dialog box.
- The Compiler's messages contain information about average and peak interconnect usage. Peak interconnect usage over 75%, or average interconnect usage over 60%, can indicate difficulties fitting your design. Similarly, peak interconnect usage over 90%, or average interconnect usage over 75%, show increased chances of not getting a valid fit.
Viewing I/O Banks
Viewing High-Speed Serial Interfaces (HSSI)

Viewing the Source and Destination of Placed Nodes
The Chip Planner allows you to view the registered fan-in or fan-outs of nodes in compiled designs with the Report Registered Connections task. This report is different from the Generate Fanin/Fanout connections report in that the source and destination nodes appear without connection lines, which may obscure the view.
- In the Chip Planner, select one or more nodes.
- In the Task pane, double-click Report Registered Connections.
- Select the options from the dialog box, and click OK.
Viewing Fan-In and Fan-Out Connections of Placed Resources
-
In the Chip Planner toolbar, click the Generate Fan-In Connections
icon or the Generate Fan-Out Connections
icon.
-
To remove other connections that appear on the Chip Planner view, click the Clear Unselected Connections
icon.
Generating Immediate Fan-In and Fan-Out Connections
For example, when you view the immediate fan-in for a logic resource, you see the routing resource that drives the logic resource. You can generate immediate fan-ins and fan-outs for all logic resources and routing resources.
- To display the immediate fan-in or fan-out connections, click View > Generate Immediate Fan-In Connections or View > Generate Immediate Fan-Out Connections.
- To remove the connections displayed, use the Clear Unselected Connections icon
in the Chip Planner toolbar.
Exploring Paths in the Chip Planner
Analyzing Connections for a Path

Locate Path from the Timing Analysis Report to the Chip Planner
- Select the path you want to locate in the Timing Analysis report.
-
Right-click the path and point to
Locate Path > Locate in Chip
Planner.
The path appears in the Locate History window of the Chip Planer.Figure 38. Path List in the Locate History Window
Show Delays

For example, you can view the delay between two logic resources or between a logic resource and a routing resource.

Viewing Routing Resources
In the Locate History window, right-click a path and select Show Physical Routing to display the physical path. To adjust the display, right-click and select Zoom to Selection.

To see the rows and columns where the Fitter routed the path, right-click a path and select Highlight Routing.

Viewing Assignments in the Chip Planner
The Chip Planner displays assigned resources in a predefined color (gray, by default).
To create or move an assignment, or to make node and pin location assignments to Logic Lock regions, drag the selected resource to a new location. The Fitter applies the assignments that you create during the next place-and-route operation.
Viewing High-Speed and Low-Power Tiles in the Chip Planner
To view a power map, double-click Tasks > Core Reports > Report High-Speed/Low-Power Tiles after running the Fitter. The Chip Planner displays low-power and high-speed tiles in contrasting colors; yellow tiles operate in a high-speed mode, while blue tiles operate in a low-power mode.
Logic Lock Regions
Logic Lock regions do not have preservation attributes, just boundaries and reservation of logic resources. You can use Intel® Quartus® Prime Pro Edition software to implement fully hierarchical Logic Lock region assignments.
A Logic Lock region is composed of two elements:
- Placement Region: Constrains logic to a specific area of the device; the Fitter places the logic in the region you specify. If you designate a region as Reserved, the Fitter cannot place other logic in the region.
- Routing Region: Constrains routing to a specific area. By default, routing regions are unconstrained. The routing region must encompass the placement region. A routing region cannot be reserved. For more details, refer to Defining Routing Regions.
Attributes of a Logic Lock Region
The following table lists the attributes of a Logic Lock region. In the Intel® Quartus® Prime software, the Logic Lock Regions window displays the attributes of all the Logic Lock regions in the design.
Name | Value | Behavior |
---|---|---|
Width | Number of columns |
Specifies the width of the Logic Lock region. If Size/State is set to Auto/Floating, the attribute is set to Undetermined. |
Height | Number of rows |
Specifies the height of the Logic Lock region. If Size/State is set to Auto/Floating, the attribute is set to Undetermined. |
Origin | Any Floorplan Location | Specifies the location of the Logic Lock region on the floorplan. The origin is at the lower left corner of the Logic Lock region. |
Reserved | Off | On | Prevents the Fitter from placing other logic in the region. You cannot apply the Reserved assignment to routing regions. |
Core-Only | Off | On | Excludes periphery resources from a region. Unlike the Intel® Quartus® Prime Standard Edition software, Intel® Quartus® Prime Pro Edition region assignments apply to periphery resources by default. If the region is designated as Reserved and Core Only, periphery resources are not reserved from the region. |
Size/State | Fixed/Locked | Auto/Floating | Specifies whether you or the Fitter determine the size and
placement of the Logic Lock region.
|
Routing Region | Unconstrained | Whole Chip | Fixed with Expansion | Custom | Type of routing region. For more details, refer to Defining Routing Regions. |
Migrating Assignments between Intel Quartus Prime Standard Edition and Intel Quartus Prime Pro Edition
Creating Logic Lock Regions
Creating Logic Lock Regions with the Chip Planner
- Click View > Logic Lock Regions > Create Logic Lock Region
- Click and drag on the Chip Planner floorplan to create a region of your preferred location and size
After you create the region, you can define the region shape and then assign a single entity to the region. The order that you assign the entity or define the shape does not matter.
Creating Logic Lock Regions with the Project Navigator
- Perform either a full compilation or analysis and elaboration on the design.
- If the Project Navigator is not already open, click View > Utility Windows > Project Navigator. The Project Navigator displays the hierarchy of the design.
- With the design hierarchy fully expanded, right-click any design entity, and click Create New Logic Lock Region.
- Assign the entity to the new region.
The new region has the same name as the entity.
Creating Logic Lock Regions with the Logic Lock Regions Window
- Click Assignments > Logic Lock Regions Window.
- In the Logic Lock Regions window, click <<new>>.
After you create the region, you can define the region shape and then assign a single entity to the region. The order that you assign the entity or define the shape does not matter.
Defining Routing Regions
Valid routing region options are:
Option |
Description |
---|---|
Unconstrained (default) | Allows the fitter to use any available routes on the device. |
Whole Chip | Same as Unconstrained, but writes the constraint in the Intel® Quartus® Prime settings file (.qsf). |
Fixed with Expansion | Follows the outline of the placement region. The routing region scales by a number of rows/cols larger than the placement region. |
Custom | Allows you to make a custom shape routing region around the Logic Lock region. When you select the Custom option, the placement and routing regions move independently in the Chip Planner. In this case, move the placement and routing regions by selecting both using the Shift key. |
Considerations on Using Auto Sized Regions
- Auto/Floating regions cannot be reserved.
- Verify that your Logic Lock region is not empty. If you do not assign any instance to the region, the Fitter reduces the size to 0 by 0, making the region invalid.
-
The region may or may not be associated with a partition. When
you combine partitions with
Auto/Floating
Size/State
Logic Lock regions, you get flexibility to
solve your particular fitting challenges. However, every constraint that you add
reduces the solutions available, and too many constraints can result in the
Fitter not finding a solution. Some cases are:
- If a partition is preserved at synthesis or not preserved, the Logic Lock region confines the logic to a specific area, allowing the Fitter to optimize the logic within the partition, and optimize the placement within the Logic Lock region.
- If a partition is preserved at placement, routed, or final; a Logic Lock region is not an effective placement boundary, because the location of the partition's logic is fixed.
- However, if the Logic Lock region is reserved, the Fitter avoids placing other logic in the area, which can help you reduce resource congestion.
-
Once the outcome of the Logic Lock region meets your specification, you can:
- Convert the Logic Lock region to Fixed/Locked Size/State.
- Leave the Logic Lock region with Auto/Floating Size/State attribute and use the region as a “keep together” type of function.
- If the Logic Lock region is also a partition, you can preserve the place and route through the partition and remove the Logic Lock region entirely.
Customizing the Shape of Logic Lock Regions
Adding a New Shape to a Logic Lock Region
- Select the Logic Lock region.
-
In the Navigation
toolbar, click the Add Logic Lock Region icon
.
-
Click and drag to generate the shape you want to add. The new
shape merges automatically with the selected Logic Lock region.
Attention: If you selected more than one region, the operation appends the new shape to all them.
Subtracting Shape from Logic Lock Region
- Select the Logic Lock region.
-
In the Navigation
toolbar, click the Subtract Logic Lock Region icon
.
-
Click and drag the shape you want to subtract. The modified
region displays automatically.
The operation performs in all selected regions.
Merging Logic Lock Regions
- Ensure that no more than one of the regions that you intend to merge has logic assignments.
- Arrange the regions into the locations where you want the resultant region.
- Select all the individual regions that you want to merge by clicking each of them while pressing the Shift key.
-
Right-click the title bar of any of
the selected Logic Lock regions and select
Logic Lock Regions > Merge Logic Lock Region. The individual regions that you select merge to create a single
new region.
If you select multiple named regions, the Merge Logic Lock Region option is deactivated.
Noncontiguous Logic Lock Regions

Placing Device Resources into Logic Lock Regions
You can assign an entity in the design to only one Logic Lock region, but the entity can inherit regions by hierarchy. This hierarchy allows a reserved region to have a sub region without reserving the resources in the sub region.
If a Logic Lock region boundary includes part of a device resource, the Intel® Quartus® Prime software allocates the entire resource to that Logic Lock region.
To add an instance using the Logic Lock Region window, right-click the region and select Logic Lock Properties > Add. Alternatively, in the Intel® Quartus® Prime software you can drag entities from the Hierarchy viewer into a Logic Lock region's name field in the Logic Lock Regions Window.
Empty Logic Lock Regions
Some reasons to use empty Logic Lock regions are:
- Preliminary floorplanning.
- Complex incremental builds.
- Team based design and interconnect logic.
- Confining logic placements.
Since Logic Lock regions do not reserve any routing resources, the Fitter may use the area for routing purposes.
Use the Core Only attribute for empty Logic Lock regions. When you include periphery resources in empty regions, you restrict the periphery component placement, which can result in a no fit design. After you name the empty region, you can perform the same manipulations as with any populated Logic Lock Region.

The figure shows an empty Logic Lock region and the logic around it. However, some IOs, HSSIO, and PLLs are in the empty region. This placement happens because the output port connects to the IO, and the IO is always part of the root_partition (top-level partition).
Pin Assignment
A Logic Lock region incorporates all device resources within its boundaries, including memory and pins. The Intel® Quartus® Prime Pro Edition software does not include pins automatically when you assign an entity to a region, unless the Core Only attribute is off.
You can manually assign pins to Logic Lock regions; however, this placement puts location constraints on the region. The software only obeys pin assignments to locked regions that border the periphery of the device. The locked regions must include the I/O pins as resources.
Reserved Logic Lock Regions
The Intel® Quartus® Prime software honors all entity and node assignments to Logic Lock regions. Occasionally entities and nodes do not occupy an entire region, which leaves some of the region’s resources unoccupied.
To increase the region’s resource utilization and performance, Intel® Quartus® Prime software by default fills the unoccupied resources with other nodes and entities that have not been assigned to another region. To prevent this behavior, turn on Reserved in the Logic Lock Regions window .
Virtual Pins
When you apply the Virtual Pin assignment to an input pin, the pin no longer appears as an FPGA pin; the Compiler fixes the virtual pin to GND in the design. The virtual pin is not a floating node.
Use virtual pins only for I/O elements in lower-level design entities that become nodes after you import the entity to the top-level design; for example, when compiling a partial design.
In the top-level design, you connect these virtual pins to an internal node of another module. By making assignments to virtual pins, you can place those pins in the same location or region on the device as that of the corresponding internal nodes in the top-level module. You can use the Virtual Pin option when compiling a Logic Lock module with more pins than the target device allows. The Virtual Pin option can enable timing analysis of a design module that more closely matches the performance of the module after you integrate it into the top-level design.
To display all assigned virtual pins in the design with the Node Finder, you can set Filter Type to Pins: Virtual. To access the Node Finder from the Assignment Editor, double-click the To field; when the arrow appears on the right side of the field, click and select Node Finder.
Example: Placement Best Practices for Intel Arria 10 FPGAs
This example describes how I/O Columns constrain locations in Logic Lock regions in designs targeting Intel® Arria® 10 FPGAs.
- If a Logic Lock region contains a register that interface with the I/O column, place the Logic Lock region so that the region covers the I/O column and the core logic, for better access to the I/O column adjacent to the outer column edge.
-
For high speed signal, you can get best results if you place the Logic Lock region on the outside of the I/O column, because the fitter is less likely to cross the column and incur delay.
Hierarchical Regions
Logic Lock assignments follow the same precedence as other constraints and assignments.
You can assign an entity in the design to only one Logic Lock region, but the entity can inherit regions by hierarchy. This hierarchy allows a reserved region to have a sub region without reserving the resources in the sub region.
Additional Intel Quartus Prime Logic Lock Design Features
Intel Quartus Prime Revisions Feature
To use the Revisions feature, choose Project > Revisions. You can create a revision from the current design or any previously created revisions. Each revision can have an associated description. You can use revisions to organize the placement constraints created for your Logic Lock regions.
Logic Lock Regions Window
Open the Logic Lock Regions Window in the Chip Planner by clicking View > Logic Lock Window, and in Intel® Quartus® Prime by clicking Assignments > Logic Lock Window.

You can customize the Logic Lock Regions Window by dragging and dropping the columns to change their order; you can also show and hide optional columns by right-clicking any column heading and then selecting the appropriate columns in the shortcut menu.
Logic Lock Regions Properties Dialog Box
Use the Logic Lock Regions Properties dialog box to view and modify detailed information about your Logic Lock region, such as which entities and nodes are assigned to your region, and which resources are required.
To open the Logic Lock Regions Properties dialog box, right-click the region and select Logic Lock Regions Properties....
Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner
- Compile the design.
-
Open the Chip Planner and the Design Partition Planner.
- Click Tools > Chip Planner
- Click Tools > Design Partition Planner
-
In the Chip Planner
window, go to the Tasks pane, and
double-click Report Design
Partitions.
The Report Design Partitions task causes the Chip Planner to display the physical locations of design entities using the same colors that the entities displayed in the Design Partition Planner.
-
In the Chip Planner, click View > Bird's Eye View
The Bird's Eye View opens.
-
In the Design Partition Planner, drag all the larger entities
out from their parents.
Alternatively, you can right-click the entity and click Extract from Parent.The Chip Planner displays the physical placement of the entities shown in the Design Partition Planner, with consistent colors between the two tools. You can view physical placement in the Chip Planner and connectivity in the Design Partition Planner.
-
Identify entities that are unsuitable to place in Logic Lock regions:
- The Chip Planner shows an entity to be physically dispersed over noncontiguous areas of the device
- The Design Partition Planner shows an entity to have a large number of connections to other entities.
-
Return entities unsuitable to place in Logic Lock regions to their parent, by dragging
into the parent's entities.
Alternatively, right-click the entity and click Collapse to Parent
- Create a partition for each remaining entity by right-clicking the entity, and then clicking Create Design Partition.
- Create a Logic Lock region for each partition by right-clicking the partition, and then clicking Create Logic Lock Region.
Viewing Design Connectivity and Hierarchy
By default, when you open a compiled design, the Design Partition Planner displays the design as a single top-level entity, containing lower-level entities. If the Design Partition Planner has opened the design previously, the design appears in its last state.

-
To show connectivity between entities, extract entities from the
top-level entity by dragging them into the surrounding white space, or by
right-clicking an entity and clicking Extract from
Parent on the shortcut menu.
When you extract entities, Design Partition Planner draws the connection bundles between entities, showing the number of connections between pairs of entities.Figure 56. Partitioned Design with Connection Bundles
- To customize the appearance of connection bundles or to set thresholds for connection counts, click View > Bundle Configuration, and set the necessary options in the Bundle Configuration dialog box.
- To see bundles containing failing paths, open the Timing Analyzer, and then click View > Show Timing Data in the Design Partition Planner. Bundles containing failing paths are displayed in red, as are entities having nodes that reside on failing paths.
- To see detailed information about the connections in a bundle, right-click the bundle, and then click Bundle Properties to open the Bundle Properties dialog box.
-
To switch between connectivity display mode and hierarchical
display mode, click View > Hierarchy Display. Alternatively, click and hold the hierarchy icon
in the top-left corner of any entity to switch temporarily to a hierarchy display.
Scripting Support
Creating Logic Lock Assignments with Tcl commands
Create or Modify a Placement Region
You can create the Logic Lock region from the GUI, or add the region directly to the QSF. The QSF entry contains the X/Y coordinates of the vertices and the Placement Region name.
The following assignment creates a new placement region with bounding box coordinates X46 Y36 X65 Y49:
set_instance_assignment -name PLACE_REGION "X46 Y36 X65 Y49" -to <node names>
- You can use the same command format to modify an existing assignment.
- To specify a non-rectangular or disjoint region, use a semicolon (;) as the delimiter between two or more bounding boxes.
- Assign multiple instances to the same region with multiple PLACE_REGION instance assignments.
Create or Modify a Routing Region
The following assignment creates a routing region with bounding box coordinates X5 Y5 X30 Y30:
set_instance_assignment -name ROUTE_REGION -to <node names> "X5 Y5 X30 Y30"
- You can use the same command format to modify an existing assignment.
- All instances with a routing region assignment must have a respective placement region; the routing region must fully contain the placement region.
Specify a Region as Reserved
The following assignment reserves an existing region:
set_instance_assignment -name <instance name> RESERVE_PLACE_REGION -to <node names> ON
- You can only reserve placement regions.
Specify a Region as Core Only
By default, the Intel® Quartus® Prime Pro Edition software includes pins in Logic Lock assignments. To specify a region as core only (that is, periphery logic in the instance that is not constrained), use the following assignment:
set_instance_assignment -name <instance name> CORE_ONLY_PLACE_REGION -to <node names> ON
Assigning Virtual Pins with a Tcl command
Use the following Tcl command to turn on the virtual pin setting for a pin called my_pin:
set_instance_assignment -name VIRTUAL_PIN ON -to my_pin
Logic Lock Region Assignment Examples
Assign Rectangular Logic Lock Region
Assigns a rectangular Logic Lock region to a lower right corner location of (10,10), and an upper right corner of (20,20) inclusive.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20"
Assign Non-Rectangular Logic Lock Region
Assigns instance with full hierarchical path "x|y|z" to non-rectangular L-shaped Logic Lock region. The software treats each set of four numbers as a new box.
set_instance_assignment –name PLACE_REGION –to x|y|z "X10 Y10 X20 Y50; X20 Y10 X50 Y20"
Assign Subordinate Logic Lock Instances
By default, the Intel® Quartus® Prime software constrains every child instance to the Logic Lock region of its parent. Any constraint to a child instance intersects with the constraint of its ancestors. For example, in the following example, all logic beneath “a|b|c|d” constrains to box (10,10), (15,15), and not (0,0), (15,15). This result occurs because the child constraint intersects with the parent constraint.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20" set_instance_assignment –name PLACE_REGION –to a|b|c|d "X0 Y0 X15 Y15"
Assign Multiple Logic Lock Instances
By default, a Logic Lock region constraint allows logic from other instances to share the same region. These assignments place instance c and instance g in the same location. This strategy is useful if instance c and instance g are heavily interacting.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20" set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X20 Y20"
Assigned Reserved Logic Lock Regions
Optionally reserve an entire Logic Lock region for one instance and any of its subordinate instances.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20" set_instance_assignment –name RESERVE_PLACE_REGION –to a|b|c ON # The following assignment causes an error. The logic in e|f|g is not # legally placeable anywhere: # set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X20 Y20" # The following assignment does *not* cause an error, but is effectively # constrained to the box (20,10), (30,20), since the (10,10),(20,20) box is reserved # for a|b|c set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X30 Y20"
Analyzing and Optimizing the Design Floorplan Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 |
|
2018.05.07 | 18.0.0 |
|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.02 | 16.0.0 | Updated information on creating LogicLock Plus regions. |
2015.11.02 | 15.1.0 |
|
2015.05.04 | 15.0.0 | Added information about color coding of LogicLock regions. |
2014.12.15 | 14.1.0 | Updated description of Virtual Pins assignment to clarify that assigned input is not available. |
June 2014 | 14.0.0 | Updated format |
November 2013 | 13.1.0 | Removed HardCopy device information. |
May 2013 | 13.0.0 | Updated “Viewing Routing Congestion” section Updated references to Quartus UI controls for the Chip Planner |
June 2012 | 12.0.0 | Removed survey link. |
November 2011 | 11.0.1 | Template update. |
May 2011 | 11.0.0 |
|
December 2010 | 10.1.0 |
|
July 2010 | 10.0.0 |
|
November 2009 | 9.1.0 |
|
May 2008 | 8.0.0 |
|
Intel Quartus Prime Pro Edition User Guides
Refer to the following user guides for comprehensive information on all phases of the Intel® Quartus® Prime Pro Edition FPGA design flow.