Tone Mapping Operator (TMO) Intel® FPGA IP
Tone Mapping Operator (TMO) Intel® FPGA IP corrects poorly exposed images andvideo to reveal invisible detail.
TMO Intel® FPGA IP Product Brief ›
Video and Vision Processing Suite Intel® FPGA IP User Guide ›
Tone Mapping Operator (TMO) Intel® FPGA IP
Overview
The TMO Intel FPGA IP modifies the contrast of a video stream to improve visibility in a wide variety of applications, such as medical imaging, video conferencing, daylight projection, security cameras, and machine vision. The IP is tile-based to take account of local exposure variations, improving the visibility of latent image detail to enhance and ease the overall viewing experience. The TMO IP core accepts RGB-format video input as an AXI4-Stream, statistically analyzes the image luminance (locally and globally) and dynamically adjusts image components to improve overall image contrast. These operations enhance underexposed and overexposed imagery to fully utilize the available dynamic range. The TMO IP requires an external processor, such as the Nios® II processor FPGA softcore, to allow configuration of TMO IP blocks and take measurements via the register bus.
Features
- Multi-tile local image statistics analysis
- Support for 8, 10 and 12 bit per color component
- Support up to 4 pixels in parallel per clock processing
- Low subframe latency (~ 100 clock cycles)
- Support resolutions up to 4K at 60 fps on Intel® C10/A10/S10 FPGAs and up to 8K at 60 fps on Intel® Agilex™FPGAs
- Low FPGA resource utilization
- AXI4-Stream video I/O interface
- AXI4-Stream ↔ Avalon® streaming interface Protocol Converters
- Avalon® memory mapped CPU control and memory interfaces
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2021 |
Latest version of Intel® Quartus® design software supported |
21.3 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following:
|
Yes |
Any additional customer deliverables provided with IP |
Testbench and design example |
Parameterization GUI allowing end user to configure IP |
Yes |
IP core is enabled for Intel FPGA IP Evaluation Mode Support |
Yes |
Source language |
Verilog |
Testbench language |
Verilog |
Software drivers provided |
Yes |
Driver OS Support |
Bare metal |
Implementation |
|
User interface |
Intel® FPGA Streaming Video Protocol, Intel® Avalon® Memory-Mapped |
IP-XACT metadata |
No |
Verification |
|
Simulators supported |
VCS,VCS MX, Active-HDL, Riviera-PRO, Xcelium, Questa-Intel® FPGA Edition, Questa |
Hardware validated |
Intel® Arria® 10 GX |
Industry-standard compliance testing performed |
No |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N/A |
Interoperability |
|
IP has undergone interoperability testing |
Yes |
If yes, on which Intel FPGA device(s) |
Intel® Cyclone® 10, Intel Arria® 10, Intel Straitix® 10, Intel Agilex™ |
Interoperability reports available |
No |
Design Example
Based on the Intel® Arria® 10 UHD HDMI 2.0 Video Format Conversion design with a simplified video pipeline and additional controls to operate and program the IP.
Need Help with Your Design?
The Intel® FPGA design services team have developed a pool of expertise and a wealth of intellectual property (IP) to solve customer design challenges in the areas of intelligent video and vision processing. Our experienced and skilled designers are motivated to meet your design needs with the most efficient and innovative solutions, using our library of highly optimized and proven IP. We cover a wide variety of applications ranging from high-volume consumer electronics to mid-volume specialist design in markets including—but not limited to—medical imaging, ProAV, industrial, military, and broadcast.
Related Links
Documentation
White Paper
Development Boards
Recursos adicionales
Encontrar PI
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IP Base Suite
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I-Tested
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