Cyclone® IV FPGAs
The Cyclone® IV FPGA family extends the Intel® Cyclone® FPGA series leadership in providing the market's lowest cost, lowest power FPGAs, now with a transceiver variant. Ideal for high-volume, cost-sensitive applications, Cyclone® IV FPGAs enable you to meet increasing bandwidth requirements while lowering costs.
Cyclone® IV FPGAs
Lower Your System Costs
All Cyclone® IV FPGAs require only two power supplies for operation, simplifying your power distribution network and saving you board costs, board space, and design time. For Cyclone® IV GX FPGAs, the cost savings are further increased. With the introduction of integrated transceivers on the leading low-power Cyclone® IV FPGA architecture, you get cost savings through simplified board design and integration. Furthermore, the flexibility of the transceiver clocking architecture allows you to implement multiple protocols while fully utilizing all available transceiver resources. The integration and flexibility of the Cyclone® IV GX FPGA enables you to design in a smaller, lower cost device, lowering your total system costs.
Reduce Power Consumption
Built on an optimized 60-nm low-power process, Cyclone® IV E FPGAs extend the low-power leadership of previous-generation Cyclone® III FPGAs. The latest generation devices reduce core voltage, which lowers total power by 25 percent compared to the predecessor. With Cyclone® IV GX transceiver FPGAs, you can build a PCI Express* to Gigabit Ethernet bridge for less than 1.5 watts.
Intel's Cyclone® IV FPGAs are optimized for the lowest power consumption, helping you better manage thermal requirements. As a result, you can reduce or eliminate system cooling costs and also extend battery life for handheld applications.
Cyclone® IV FPGA Power Consumption
The Cyclone® IV FPGA family demonstrates Intel’s leadership in offering power-efficient FPGAs. With enhanced architecture and silicon, advanced semiconductor process technology, and power management tools, power consumption for Cyclone® IV FPGAs has been reduced by up to 25 percent compared to Cyclone® III FPGAs. The result is the lowest power consumption of any comparable FPGA.
The following figure shows the static power consumption of Cyclone® IV E devices at 85°C junction temperature. The smallest Cyclone® IV EP4CE6 device consumes as little as 38 mW at 85°C and the largest Cyclone® IV EP4CE115 device consumes as little as 163 mW static power at 85°C.
Benefits of Low Power Consumption
Reducing the power consumption of programmable logic devices carries far-reaching benefits for many applications. However, lower power consumption is only one aspect of system power. The following figure shows that Cyclone® IV GX FPGAs lower FPGA power consumption by an average of 30 percent.
Silicon and Architectural Optimizations
Static power can increase dramatically with the sub-micron semiconductor process if no power-reduction strategies are employed. Static power consumption rises at submicron process technologies largely because of increases in leakage current subthreshold leakage.
Intel has taken significant steps to reduce static power in Cyclone® IV FPGAs. By employing a low-power (LP) process technology traditionally used by major semiconductor manufacturers for handset components, Intel has minimized the leakage current for low static power. The smaller geometries made possible by this advanced process, combined with architectural optimizations, enable Cyclone® IV FPGAs to keep dynamic and static power consumption to a minimum. The process and architectural enhancements that Intel employs with Cyclone® IV FPGAs includes the use of low-k dielectrics, variable channel lengths and oxide thicknesses, and multiple transistor threshold voltages.
Accurate Power Estimation and Analysis
Intel supports power estimation and analysis, from design concept through implementation, with the most accurate and complete power management design tools. Intel is also the only programmable logic vendor that offers up to 125°C and worst-case silicon power estimates for the low-cost FPGA families throughout its tool suite. Intel offers the following power estimation and analysis resources:
- Cyclone® IV early power estimator.
- Intel® Quartus® Prime power analysis and optimization technology.
- Power Management Resource Center.
Use the early power estimator (EPE) during the design concept phase and the Power Analyzer during design implementation. The EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization.
The Power Analyzer is a far more detailed power analysis tool that uses actual design placement and routing and logic configuration. The tool can use simulated waveforms to very accurately estimate dynamic power. The power analyzer, in aggregate, usually provides ± 10 percent accuracy when used with accurate design information. The Intel® Quartus® Prime power models closely correlate to actual silicon measurements.
Intel uses more than 5,000 different test configurations to measure the power of individual components within an Intel® Cyclone® series FPGA. Each configuration is focused on measuring a single circuit component of the FPGA in a specific configuration.
Intel® Quartus® Prime Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow.
Intel is a leader in bringing power optimization into the design flow. Intel® Quartus® Prime software power optimization tools automatically use the Cyclone® IV FPGA architecture capabilities to reduce up to 25 percent lower dynamic power consumption compared to Cyclone® III FPGAs.
The Intel® Quartus® Prime development software has many automatic power optimizations that are transparent to the designer but provide optimal utilization of the FPGA architecture to minimize power. For example, with Intel® Quartus® Prime software, you can:
- Transform major functional blocks.
- Map user RAMs so they use less power.
- Restructure logic to reduce dynamic power.
- Correctly select logic inputs to minimize capacitance on high-toggling nets.
- Reduce area and wiring demand for core logic to minimize dynamic power in routing.
- Modify placement to reduce clocking power.
Cyclone® IV E Typical Static Power Consumption
System Power Savings using Cyclone® IV GX FPGAs
The combination of increased integration and a low-power Cyclone® IV GX FPGA results in significant system-level benefits for a variety of applications:
- Portable or handheld battery-powered devices.
- Space-constrained and other thermally challenging environments.
- Price-sensitive applications where cooling systems are not cost effective.
For more information on lowering your total cost of ownership and achieving higher reliability in your designs, refer to the Decrease Total System Costs with Industry's Lowest Cost, Lowest Power FPGAs White Paper (PDF).
Cyclone® IV FPGAs continue the Intel® Cyclone® series tradition of offering an unprecedented combination of low power, high functionality, and low cost. Cyclone® IV GX FPGAs feature integrated transceivers at up to 3.125 Gbps.
The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs). Both GX and E devices have four general-purpose PLLs located at each corner of the die. The Cyclone® IV GX FPGA has I/O elements at the top, bottom, and right sides of the die, while the Cyclone® IV E FPGA has I/Os on all four sides of the die. The left side of the Cyclone® IV GX FPGA die has up to eight transceivers in two quads consisting of four transceivers per quad. The top and bottom of each transceiver quad features a multi-purpose PLL (MPLL) that the transceiver or the FPGA fabric can use.
Cyclone® IV GX FPGAs are built with Intel's proven GX transceiver technology, known for excellent jitter performance and superior signal integrity. The PCI-SIG-compliant transceiver variant supports a wide variety of serial protocols. Cyclone® IV GX FPGAs also feature the only hard intellectual property (IP) block for PCI Express x1, x2, and x4 in rootport and endpoint configurations.