® Intel 81341 and Intel Processors Datasheet Product Features � Intel® 81341 I/O Processor contains one � ® integrated Intel XScale processor � � Intel® 81342 I/O Processor contains two ® integrated Intel XScale processors � Processor features — 800 MHz and 1.2 GHz � — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way � Set Associative, NRU Replacement � Algorithm, Lockable � — Unified Level 2 Cache: 512 KByte Set Associative, NRU Replacement Algorithm — 128-Entry Branch Target Buffer � — 8-Entry Write Buffer — 8-Entry Fill and Pend Buffer � Internal Bus 400 MHz/128-bit � � Can support either PCI-X or PCI Express* as an endpoint � Support for PCI Express* Lane Widths of x1, x2, x4, x8 � Multi-ported Memory Controller — Intel XScale® processor inputs and north internal bus, south internal bus and ADMA � input ports — PC3200 and PC4300 Double Data Rate � (DDR2 400, DDR2 533) — Up to 4 GB of 64-bit DDR2 400, DDR2 533 — Optional Single-bit Error Correction, Multi- bit Detection ECC Support — Supports Registered and Unbuffered DDR2 Memory — 36-bit Addressable — 32-bit Memory Support ® 81342 I/O Integrated SRAM Memory Controller (1 MB) Address Translation Unit — 2 KB or 4 KB Outbound Read Queue — 4 KB Outbound Write Queue — 4 KB Inbound Read and Write Queue Two Programmable 32-bit Timers and Watchdog Timer Sixteen General Purpose I/O Pins 2 Three I C Bus Interface Units Two UART (16550) Units — 64 Byte Receive and Transmit FIFOs — 4 pin Master/Slave Capable Peripheral Bus Interface — 8-, 16-bit Data Bus with Two Chip Selects — 25 Demultiplexed Address Lines Interrupt Controller Unit — Four Priority Levels — Interrupt Pending Register — Vector Generation — 16 External Interrupt Pins with High Priority Interrupt (HPI#) 1357-ball, Flip Chip Ball Grid Array (FCBGA), 37.5 mm x 37.5 mm and 1.0 mm ball pitch Application DMA Controller — Three Independent Channels Connected to the MCU and the South Internal Bus — 4 KByte Data Transfer Queue — CRC 32C Calculation — Performs Optional XOR on Read Data Order Number: 315039-003US December 2007

® 
Intel 81341 and Intel 
Processors 
Datasheet 
Product Features 
� Intel® 81341 I/O Processor contains one � 
® 
integrated Intel XScale processor � 
� Intel® 81342 I/O Processor contains two 
® 
integrated Intel XScale processors 
� Processor features 
— 800 MHz and 1.2 GHz � 
— ARM* V5TE Compliant 
— Instruction/Data Cache: 32 KByte, 4-way � 
Set Associative, NRU Replacement � 
Algorithm, Lockable � 
— Unified Level 2 Cache: 512 KByte Set 
Associative, NRU Replacement Algorithm 
— 128-Entry Branch Target Buffer � 
— 8-Entry Write Buffer 
— 8-Entry Fill and Pend Buffer 
� Internal Bus 400 MHz/128-bit � 
� Can support either PCI-X or PCI Express* as 
an endpoint 
� Support for PCI Express* Lane Widths of x1, 
x2, x4, x8 
� Multi-ported Memory Controller 
— Intel XScale® processor inputs and north 
internal bus, south internal bus and ADMA � 
input ports 
— PC3200 and PC4300 Double Data Rate � 
(DDR2 400, DDR2 533) 
— Up to 4 GB of 64-bit DDR2 400, DDR2 533 
— Optional Single-bit Error Correction, Multi- 
bit Detection ECC Support 
— Supports Registered and Unbuffered DDR2 
Memory 
— 36-bit Addressable 
— 32-bit Memory Support

 ® 81342 I/O 
Integrated SRAM Memory Controller (1 MB) 
Address Translation Unit 
— 2 KB or 4 KB Outbound Read Queue 
— 4 KB Outbound Write Queue 
— 4 KB Inbound Read and Write Queue 
Two Programmable 32-bit Timers and 
Watchdog Timer 
Sixteen General Purpose I/O Pins 
2 
Three I C Bus Interface Units 
Two UART (16550) Units 
— 64 Byte Receive and Transmit FIFOs 
— 4 pin Master/Slave Capable 
Peripheral Bus Interface 
— 8-, 16-bit Data Bus with Two Chip Selects 
— 25 Demultiplexed Address Lines 
Interrupt Controller Unit 
— Four Priority Levels 
— Interrupt Pending Register 
— Vector Generation 
— 16 External Interrupt Pins with High Priority 
Interrupt (HPI#) 
1357-ball, Flip Chip Ball Grid Array (FCBGA), 
37.5 mm x 37.5 mm and 1.0 mm ball pitch 
Application DMA Controller 
— Three Independent Channels Connected to 
the MCU and the South Internal Bus 
— 4 KByte Data Transfer Queue 
— CRC 32C Calculation 
— Performs Optional XOR on Read Data 
Order Number: 315039-003US 
December 2007

® Intel 81341 and Intel Processors Datasheet Product Features � Intel® 81341 I/O Processor contains one � ® integrated Intel XScale processor � � Intel® 81342 I/O Processor contains two ® integrated Intel XScale processors � Processor features — 800 MHz and 1.2 GHz � — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way � Set Associative, NRU Replacement � Algorithm, Lockable � — Unified Level 2 Cache: 512 KByte Set Associative, NRU Replacement Algorithm — 128-Entry Branch Target Buffer � — 8-Entry Write Buffer — 8-Entry Fill and Pend Buffer � Internal Bus 400 MHz/128-bit � � Can support either PCI-X or PCI Express* as an endpoint � Support for PCI Express* Lane Widths of x1, x2, x4, x8 � Multi-ported Memory Controller — Intel XScale® processor inputs and north internal bus, south internal bus and ADMA � input ports — PC3200 and PC4300 Double Data Rate � (DDR2 400, DDR2 533) — Up to 4 GB of 64-bit DDR2 400, DDR2 533 — Optional Single-bit Error Correction, Multi- bit Detection ECC Support — Supports Registered and Unbuffered DDR2 Memory — 36-bit Addressable — 32-bit Memory Support ® 81342 I/O Integrated SRAM Memory Controller (1 MB) Address Translation Unit — 2 KB or 4 KB Outbound Read Queue — 4 KB Outbound Write Queue — 4 KB Inbound Read and Write Queue Two Programmable 32-bit Timers and Watchdog Timer Sixteen General Purpose I/O Pins 2 Three I C Bus Interface Units Two UART (16550) Units — 64 Byte Receive and Transmit FIFOs — 4 pin Master/Slave Capable Peripheral Bus Interface — 8-, 16-bit Data Bus with Two Chip Selects — 25 Demultiplexed Address Lines Interrupt Controller Unit — Four Priority Levels — Interrupt Pending Register — Vector Generation — 16 External Interrupt Pins with High Priority Interrupt (HPI#) 1357-ball, Flip Chip Ball Grid Array (FCBGA), 37.5 mm x 37.5 mm and 1.0 mm ball pitch Application DMA Controller — Three Independent Channels Connected to the MCU and the South Internal Bus — 4 KByte Data Transfer Queue — CRC 32C Calculation — Performs Optional XOR on Read Data Order Number: 315039-003US December 2007

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All rights reserved. ® Intel 81341 and 81342 I/O Processors Datasheet December 2007 2 Order Number: 315039-003US ® Contents—Intel 81341 and 81342 Contents 1.0 Introduction ..............................................................................................................7 1.1 About This Document...........................................................................................7 1.1.1 Terminology ............................................................................................7 1.1.2 Other Relevant Documents ........................................................................7 2.0 Features ....................................................................................................................9 ® ® 2.1 Intel 81341 and Intel 81342 Read the full ® Intel 81341 and Intel Processors Datasheet Product Features � Intel® 81341 I/O Processor contains one � ® integrated Intel XScale processor � � Intel® 81342 I/O Processor contains two ® integrated Intel XScale processors � Processor features — 800 MHz and 1.2 GHz � — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way � Set Associative, NRU Replacement � Algorithm, Lockable � — Unified Level 2 Cache: 512 KByte Set Associative, NRU Replacement Algorithm — 128-Entry Branch Target Buffer � — 8-Entry Write Buffer — 8-Entry Fill and Pend Buffer � Internal Bus 400 MHz/128-bit � � Can support either PCI-X or PCI Express* as an endpoint � Support for PCI Express* Lane Widths of x1, x2, x4, x8 � Multi-ported Memory Controller — Intel XScale® processor inputs and north internal bus, south internal bus and ADMA � input ports — PC3200 and PC4300 Double Data Rate � (DDR2 400, DDR2 533) — Up to 4 GB of 64-bit DDR2 400, DDR2 533 — Optional Single-bit Error Correction, Multi- bit Detection ECC Support — Supports Registered and Unbuffered DDR2 Memory — 36-bit Addressable — 32-bit Memory Support ® 81342 I/O Integrated SRAM Memory Controller (1 MB) Address Translation Unit — 2 KB or 4 KB Outbound Read Queue — 4 KB Outbound Write Queue — 4 KB Inbound Read and Write Queue Two Programmable 32-bit Timers and Watchdog Timer Sixteen General Purpose I/O Pins 2 Three I C Bus Interface Units Two UART (16550) Units — 64 Byte Receive and Transmit FIFOs — 4 pin Master/Slave Capable Peripheral Bus Interface — 8-, 16-bit Data Bus with Two Chip Selects — 25 Demultiplexed Address Lines Interrupt Controller Unit — Four Priority Levels — Interrupt Pending Register — Vector Generation — 16 External Interrupt Pins with High Priority Interrupt (HPI#) 1357-ball, Flip Chip Ball Grid Array (FCBGA), 37.5 mm x 37.5 mm and 1.0 mm ball pitch Application DMA Controller — Three Independent Channels Connected to the MCU and the South Internal Bus — 4 KByte Data Transfer Queue — CRC 32C Calculation — Performs Optional XOR on Read Data Order Number: 315039-003US December 2007.

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