This webcast looks at how mitigating soft errors through error correction code (ECC) can improve your embedded designs. (Hans Spanjaart, Sr. technical marketing manager)
Watch this webcast to find out about a new technology for FPGAs called OpenCL™ platform. You'll learn about the market drivers and embedded technology enablers, the benefits of using FPGAs as hardware accelerators, and how OpenCL™ platform fits in an FPGA-based design environment. (Jordon Inkeles, Sr. manager, Software and DSP)
Watch this webcast to find out how a customizable solution and quick intellectual property (IP) integration helps you build your video design faster – whether for simple format conversion or advanced digital video processing. (Richard Yang, Sr. product marketing engineer)
When choosing your FPGA design software, be sure to consider compile time, a key productivity advantage. In this webcast, you'll learn how the Intel® Quartus® Prime Design Software delivers a 2X to 3X compile time advantage over competitive software. (Richard Yang, product marketing engineer)
Learn about key innovations in Stratix® V FPGAs that address bandwidth and power challenges in high-end systems designs. Embedded hard copy blocks, power-efficient 28-Gbps transceivers, and software power optimization are just a few of the features that will help you balance bandwidth, power, and cost requirements. (Frank Yazbeck, Sr. technical marketing staff)
Developing network surveillance cameras? Watch this webcast to see how an FPGA provides a single-chip platform for these cameras. Learn about a full video surveillance solution that includes silicon and intellectual property. Image processing for wide dynamic range (WDR) CMOS sensors (Judd Heape, Sr. strategic marketing manager, Industrial Business Unit)
See how DSP Builder for Intel® FPGAs (Advanced Blockset) lets you optimize your large design's performance while reducing design iterations. Using a sensor (radar) front-end design example on a large FPGA, you'll see how DSP Builder simplifies and speeds your design process. (Michael Parker, Sr. DSP technical marketing manager)
Partner Solution Demos
Intel's synthetic-aperture radar (SAR) back-end processing demo on Intel® Arria® 10 devices utilizing hard floating-point DSP blocks and OpenCL™ platform.
Neuromorphic Processor in Intel® Arria® 10 SoC FPGA for 100X performance gain for cybersecurity.
Hardware and Software Security Hardened Crypto Accelerators on Intel® FPGAs and SoC.
Intel's Ultra-Wideband Channelizer on Intel® Arria® 10 FPGAs with JESD204B Interface into Multi-GSPS ADC.
Cognitive Radio Solutions from Handhelds to Rack-mount Systems with RedHawk SDR and OpenCL™ platform Hardware Acceleration.
Programmable SDR Kit on a Cyclone® V SoC FPGA and ADI AD9361 HSMC.