Introduction This project is meant to demonstrate HPS capabilities to map its IP peripheral signals to the FPGA interface The project mapped the following IP periperals to FPGA interface: - EMAC0 to on-board mii PHY - I2C0 to various on-board I2C slaves Note: This example was developed with and tested against SoC EDS 14.0b200. ==== Target Boards: - Altera Cyclone V SoC Development Board rev D. ==== Source Files The following are descriptions of the AN706 design files for this project: ghrd_top.v Top level RTL file soc_system_timing.sdc Timing constraint file an706_de_pin_assignment.tcl Pin assignment script file preloader-mkpimage.bin Generated preloader binary targeted to this project u-boot.img Modified u-boot image for EMAC0 socfpga.dtb Modified device tree for EMAC0 and I2C0 ===== Building Example Before running the example, the target executable first needs to be built. 1. Make a copy of the Cyclone V Golden Hardware Reference Design (GHRD) from your Cyclone V SoC Development Kit installation location or download the latest Cyclone V GHRD design example from the Rocketboards website to your project location. 2. Download the an706 design files provided and apply to the project according to AN706 workflow. 3. Program SD Card after with an706 design files provided. The Console panel (bottom of the UI) should detail the progress of the build and report any warnings or errors. ===== System Setup 1. Connect the USB to serial bridge to the host computer. 2. Connect the USB-BlasterII to the host computer. 3. Install the USB to serial bridge driver on the host computer if that driver is not already present. Consult documentation for the DevKit for instructions on installing the USB to serial bridge driver. 4. Install the USB-BlasterII driver on the host computer if that driver is not already present. Consult documentation for QuartusII for instructions on installing the USB-BlasterII driver. 5. Connect Ethernet Cable to the ENET1 Ethernet port. 6. Slot in SD card. ===== Running the Example After building the example and setting up the host computer system, the example can be run by following these steps. 1. Power on the board. 2. Program the FPGA sof file. 3. Warm reset to reload SD card image to the FPGA. 4. The kernel automatically enables and initializes EMAC0 and then executes the dynamic host configuration protocol (DHCP) to obtain an IP address. 5. When the boot process has completed, login as root at the kernel terminal. 6. Follow AN706 to perform test on EMAC and I2C ===== Sample output libphy: stmmac: probed eth0: PHY ID b8242825 at 0 IRQ POLL (stmmac-0:00) active eth0: PHY ID b8242825 at 1 IRQ POLL (stmmac-0:01) eth0: PHY ID 00000000 at 5 IRQ POLL (stmmac-0:05) eth0: PHY ID 00000000 at 6 IRQ POLL (stmmac-0:06) eth0: PHY ID ff5f521e at 7 IRQ POLL (stmmac-0:07) stmmac - user ID: 0x10, Synopsys ID: 0x37 ...... Configuring network interfaces... eth0: device MAC address 0e:31:21:99:96:6b udhcpc (v1.20.2) started Sending discover... libphy: stmmac-0:00 - Link is Up - 100/Full Sending discover... Sending select for 137.57.118.129... Lease of 137.57.118.129 obtained, lease time 86400 /etc/udhcpc.d/50default: Adding DNS 137.57.116.2 /etc/udhcpc.d/50default: Adding DNS 137.57.137.2 /etc/udhcpc.d/50default: Adding DNS 137.57.64.1 done.