Introduction This HardwareLibs project is meant as an example for using the ECC APIs. The project demonstrates the following ECC API features for the following components: - Onchip RAM - DMA Each component will demonstrate on the following: - Setup and enable ECC - Setup and enable ECC interrupts - Inject single and double bit errors - Single and double bit errors detection Note: This example was tested against SoC EDS 18.0. ==== Target Boards: - Altera Arria 10 SoC Development Board rev C. ==== Limitations: N/A ==== Source Files The following are descriptions of the source and header files contained in this project: ecc_demo_a10.c Contain the main, system initialization and cleanup. ecc_demo_ocram_a10.c Contain functions demonstrating ECC single and double bit injection and detection. ecc_demo_dma_a10.c Contain functions demonstrating ECC single and double bit injection and detection. alt_pt.{c,h} Contain functions to setup MMU page tables. alt_ecc_scratch_ram_get.c Contain function to be appended to alt_ecc.c during compile time. Refer Makefile for details. ===== Building Example Before running the example, the target executable first needs to be built. 1. In DS-5, build the application: 1a. Switch to the C/C++ Perspective if not already in that perspective by selecting the menu: Window >> Open Perspective >> C/C++. 1b. In the "Project Explorer" panel, right-mouse-click "Altera-SoCFPGA-HardwareLib-ECC-A10-GNU" and select "Build Project". The Console panel (bottom of the UI) should detail the progress of the build and report any warnings or errors. ===== Debugging the Example 1. Configure the FPGA with the A10 GHRD FPGA configuration file /embedded/examples/hardware/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof This can be achieved by running the following command from the Embedded Command Shell: quartus_pgm --no_banner --mode=jtag -o "p;$SOCEDS_DEST_ROOT/examples/hardware/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof" 2. Connect the USB to serial bridge to the host computer. 3. Connect the USB-BlasterII to the host computer. 4. Install the USB to serial bridge driver on the host computer if that driver is not already present. Consult documentation for the DevKit for instructions on installing the USB to serial bridge driver. 5. Install the USB-BlasterII driver on the host computer if that driver is not already present. Consult documentation for QuartusII for instructions on installing the USB-BlasterII driver. 6. In DS-5, configure the launch configuration. 6a. Select the menu: Run >> Debug Configurations... 6b. In the options on the left, expand "DS-5 Debugger" and select "Altera-SoCFPGA-HardwareLib-ECC-A10-GNU". 6c. In the "Connections" section near the bottom, click Browse. 6d. Select the appropriate USB-BlasterII to use. Multiple items will be presented if there is more than one USB-BlasterII connection attached to the host computer. 6e. Click "Apply" then "OK" to apply the USB-BlasterII selection. 6f. Click "Close" to close the Debug Configuration. Otherwise click "Debug" run the example in the debugger. Connecting to the target takes a moment to load the Bootloader, run the Bootloader, load the executable, and run executable. After the debug connection is established, the debugger will pause the execution at the main() function. Users can then set additional break points, step into, step out of, or step one line using the DS-5 debugger. Consult documentation for DS-5 for more information on debugging operations. ===== Sample output INFO: System Initialization. INFO: ECC OCRAM Demo started. INFO: Initialize and start ECC for OCRAM. INFO: Setup interrupts INFO: Setup Interrupt List [ 34 32 ]. INFO: Injecting SERR ... INFO: Error injected at 0xffe1f42c. INFO: Read OCRAM contents ... INFO [ISR]: Incrementing count for 34. INFO [ISR]: SERR occurred at 0x742c. INFO [ISR]: Clearing SERR interrupt in SysMgr. INFO: Read OCRAM content - Complete! INFO: ECC ISR for OCRAM triggered SERR condition. INFO: Injecting DERR ... INFO: Error injected at 0xffe18ccc. INFO: Read OCRAM contents ... INFO [ISR]: Incrementing count for 32. INFO [ISR]: DERR occurred at 0xccc. INFO [ISR]: Clearing DERR interrupt in SysMgr. INFO [ISR]: Incrementing count for 34. INFO [ISR]: SERR occurred at 0x742c. INFO [ISR]: Clearing SERR interrupt in SysMgr. INFO: Read OCRAM content - Complete! INFO: ECC ISR for OCRAM triggered DERR condition. INFO: Cleaning up ECC OCRAM interrupts. INFO: Cleanup Interrupt List [ 34 32 ]. INFO: ECC OCRAM Demo succeeded. INFO: ECC DMA Demo started. INFO: Initializing DMA. INFO: Channel 0 allocated. INFO: Channel state = [ALT_DMA_CHANNEL_STATE_STOPPED]. INFO: Channel 1 allocated. INFO: Channel state = [ALT_DMA_CHANNEL_STATE_STOPPED]. INFO: Setup of DMA successful. INFO: Initialize and start ECC for DMA. INFO: Setup Interrupt List [ 34 32 ]. INFO: Write to DMA MFIFO. INFO: Read from DMA MFIFO. INFO: Waiting for WFE. INFO: Inject SERR into DMA MFIFO. EVENT: Inject SERR into DMA RAM at 0. INFO: Send event. INFO [ISR]: SERR occurred at 0x0. INFO [ISR]: Clearing SERR interrupt in SysMgr. INFO: ECC ISR for DMA triggered SERR condition. INFO: Write to DMA MFIFO. INFO: Read from DMA MFIFO. INFO: Waiting for WFE. INFO: Inject DERR into DMA MFIFO. EVENT: Inject SERR into DMA RAM at 1. INFO: Send event. INFO [ISR]: DERR occurred at 0x1. INFO [ISR]: Clearing DERR interrupt in SysMgr. INFO: ECC ISR for DMA triggered DERR condition. INFO: Cleanup Interrupt List [ 34 32 ]. INFO: ECC DMA Demo succeeded. INFO: System shutdown. RESULT: All tests successful.