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High Performance 32nm Logic Technology

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High Performance 32nm Logic Technology

Abstract

A 32nm logic technology for high performance microprocessors is described. 2nd generation High-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.

Technology Overview

Continuing Moore’s law to the 32nm technology node requires difficult trade-offs in gate length, S/D contact area and contact-to-gate margins. As dimensions are reduced, less area is available for contacting S/D regions leading to potential Rext increases as well as less area for introducing strain for mobility enhancement to improve device performance. To continue the historical trends of both area and performance improvement requires novel solutions. Figure 1 shows the 32 nm node is continuing the historic trend in gate pitch.

In addition to intrinsic device performance improvement, the ability to operate at low Vcc is becoming even more critical for low power products. This paper presents a high performance, 112.5nm pitch High-k + metal gate strain enhanced technology that continues Moore’s law to the 32nm technology node and enables low Vccmin operation.

Read the full High Performance 32nm Logic Technology Paper.

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