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Challenges and Innovations in Nano‐CMOS Transistor Scaling

Presentation: Tahir Ghani (Intel) reviews traditional‐scaling, modern innovations and future challenges and options for Nano‐CMOS Transistor Scaling.

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Intel®’s 22nm Technology Moves Transistor Into the 3rd Dimension

Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.

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Intel Global Manufacturing Facts

Fact Sheet: Intel Global Manufacturing

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Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met

Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.

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Presentation: Low Power Optimize a 32nm SoC Platform Technology

Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.

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Presentation: RF CMOS Technology Scaling in High-k/Metal Gate Era

Presentation examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

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Gate Dielectric Scaling for CMOS: from SiO2/PolySi to High-K/Metal-Gate

Presentation covers SiO2 scaling, high-k/metal-gate problems, breakthroughs, and performance reports for NMOS and PMOS transistors.

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Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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