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Radio Network Layer Data Plane Processing: Paper

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Radio Network Layer Data Plane Processing: Paper

Abstract

This paper describes a software package that implements some of the workload associated with a Radio Network Layer (RNL) Data Plane pipeline. It describes techniques used for optimizing the CPU workload, and outlines the resulting benchmarks.

Introduction

Traditionally, high-performance packet processing has been implemented using application-specific hardware, typically ASICs, FPGAs, and network processors. Recent solutions utilize general purpose processors coupled with application-specific accelerators (for example, security and encryption engines). For a packet processing solution to be fit for purpose, it must provide sufficient compute performance in conjunction with a tightly coupled high-bandwidth memory I/O.

The latest multi-core embedded Intel® architecture processors provide both the required I/O bandwidth and compute resource required to support intensive packet-processing workloads. Embedded Intel architecture processors are high-performance processing machines with several cores per processor, each supporting simultaneous multithreading technology (SMT). The specific embedded Intel architecture processor used for this paper had four cores per processor with SMT. Thus, in a dual-processor configuration, 16 logical cores are available.

The processor’s Intel® QuickPath Interconnect system bus provides both high-bandwidth intra-processor and processor-to-I/O Hub chipset communication. Each processor also incorporates three DDR3 channels, providing high memory subsystem throughput.

Read the full Radio Network Layer Data Plane Processing White Paper.

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