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Interfacing I²C* Devices to SMBus Controller

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Interfacing I²C* Devices to SMBus Controller

Executive Summary
Intel includes one or more SMBus controllers as part of their chipset devices. Its primary purpose is to permit the chipset to communicate with SMBus devices such as the SPD EEPROMs* on the DIMMs, the clock driver, and various temperature sensors. Some designs incorporate I2C* slave devices on the SMBus. Being "similar" to the I2C bus, it is often difficult to program the Intel® I/O Controller Hub (ICH) SMBus controller to reliably communicate with these I2C slave devices.

The purpose of this paper is to provide details on the various SMBus cycles that the Intel ICH SMBus controller can create, and then to provide guidelines on how to "analyze" the cycles supported by I2C devices to see if they can be successfully accessed by the Intel ICH SMBus controller.

It is important to realize that sometimes it is not possible to program the SMBus controller's basic cycles to communicate with a given I2C device. The judicious use of the various blocks modes when combined with the setting of an "I2C Enable" bit (I2C_EN) (which changes the format of the some of the cycles slightly) often permits the Intel ICH SMBus controller to communicate successfully with I2C devices.

Read the full Interfacing I²C* Devices to SMBus Controller White Paper.

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