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Intel® Q35 Express Chipset for Embedded Computing: BriefProduct OverviewThe Intel® Q35 Express Chipset addresses key requirements of many embedded computing designs, including quality graphics, low-power consumption, noise reduction, manageability, data protection, and security. When combined with the Intel® Core™ microarchitecture family of processors on 45nm and 65nm process technology, the platform helps embedded equipment manufacturers deploy exceptionally responsive, high-performance, low-power systems for interactive clients—i.e. point-of-sale terminals and interactive PCs—, industrial control and automation, gaming, print imaging, and network security applications.The updated graphics memory controller hub features a low-power graphics core. With a total thermal design power (TDP) of 13 watts, and a lower idle of 5.5 watts, the Intel Q35 Express chipset provides a 50% power savings over the Intel® Q965 Express chipset (28 watts TDP). The I/O controller hub (ICH) is available in two SKUs: Intel® ICH9 and Intel ICH9 DO (digital office). A 1333 MHz system bus supports Intel® processors on 45nm.Twelve Hi-Speed USB 2.0* ports and external SATA* (eSATA) port multiplier support on both ICH SKUs provide design flexibility, while Intel® Quiet System Technology regulates system and processor fan speeds for noise reduction. Additionally, the ICH9 DO supports Intel® Active Management 3.0 for remote manageability, and Intel® Rapid Recover Technology for data protection.Read the full Intel® Q35 Express Chipset for Embedded Computing Product Brief.
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Overview: Highlights the benefits and enhancements of the platform. (v.001, May 2011)
Tech leaders discuss the power of connecting billions of devices to extract greater big data insights.
Demonstrates how to use a USB drive to boot a customer reference board to DOS. (v.1, June 2010)
Automatically change the boot up disk order to reboot in the event of failure. (v.001, Dec. 2010)
Recover and diagnose failure remotely, preventing costly downtime. (v.001, Dec. 2010)
Discusses increasing throughput for multi-core processors. (v.1, June 2009)