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Hardware Level I/O Benchmarking of PCI Express*

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Hardware Level I/O Benchmarking of PCI Express*

Executive Summary
Understanding the PCI Express* performance capabilities of embedded design is critical in selecting a solution that supports the IO requirements for the intended usage model. Theoretical bandwidth data is not sufficient since it is simply a calculation of frequency and bus width, not taking into account protocol overhead, bus/link efficiency, platform latency or bandwidth scaling across multiple IO devices.
This paper addresses how to set PCI Express* performance targets and how to collect hardware-level measurements. It begins with an overview of Intel® architecture and PCI Express architecture. Following these overviews, we focus on setting PCI Express performance targets, PCI Express measurement methodology, tuning, and interpreting results.
This paper will help the reader understand what is required to collect meaningful PCI Express performance data and what the results mean.

Read the full Hardware Level I/O Benchmarking of PCI Express* White Paper.

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