■ IEEE 802.3 10BASE-T/100BASE-TX ■ compliant physical layer interface ■ ■ IEEE 802.3u Auto-Negotiation support ■ ■ Digital Adaptive Equalization control ■ Link status interrupt capability ■ ■ XOR tree mode support ■ ■ 3-port LED support (speed, link and ■ activity) ■ 10BASE-T auto-polarity correction ■ ■ LAN Connect interface ■ 82547/82541 layout compatible ■ PHY detects polarity, MDI-X, and cable lengths. Auto MDI, MDIX crossover at all speeds a.This device is lead-free. That is, lead has not been at <1000 ppm. The Material Declaration Data Sheet, which of other Restriction on Hazardous Substances Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in “unplugged mode” (less than 50 mW) Automatic detection of “unplugged mode” 3.3 V device a Lead-free 196-pin Ball Grid Array (BGA). (Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx.) intentionally added, but lead may still exist as an impurity includes lead impurity levels and the concentration (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmark In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales repre- sentative. Additional Features ■ The 82562GZ PLC supports drop-in replacement with the 82562EZ. If it is not used as a drop-in replacement, strapping options enable new operating modes: —LED support for three logic configurations. —LAN disable function using one pin. —Increased transmit strength. ■ The receive BER performance increases the margin for cable length. ■ Return Loss performance is improved. Revision 1.4 April 2005 Revision History Revision 0.75 1.0 1.1 1.2 1.3 1.4 Revision Date May 2004 Sept 2004 Oct 2004 Nov 2004 Jan 2005 Apr 2005 Description Initial release (confidential status). Updated resistor values for RBIAS10 (new value is 619 Ω) and RBIAS100 (new value is 649 Ω) and added lead-free device information. • Updated Table 1 and Table 2 to reflect correct hardware configurations and LED logic functionality. • Corrected signal names to match design guide and reference schematics. • Added information about migrating from a 2-layer 0.36 mm wide-trace sub- strate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. • Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Package Information”. • Added a note for PHY signals RBIAS100 and RBIAS10 to Section 4.3. • Added internal/external pull-up/pull-down resistor values to the Hardware Configuration table and signal definition tables for TESTEN, ISOL_EXEC, ISOL_TI, ISOL_TCK, and ADV10/LAN_DISABLE#. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to Read the full 82562GZ 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet Product Features.