Design Guide Networking Silicon 317520-002 Revision 2.2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The product(s) described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © Intel Corporation, 2008 *Third-party brands and names are the property of their respective owners. ii 82562EZ(EX)/82547GI(EI) Dual Footprint Revision History Revision 0.25 0.75 1.0 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 Revision Date Jul 2002 Sep 2002 Oct 2002 Sep 2003 Nov 2004 Jan 2005 Jan 2005 June 2006 Feb 2007 June 2007 Jan 2008 Description Initial publication of preliminary design guide information. Published revised design guide information: • Added information on EEPROM settings • Added design checklist • Revised reference design schematic • Revised Ball Number to signal mapping Table to conform to changes in 82547EI datasheet rev 0.75 Published revised design guide information: • Added layout checklist • Updated LAN disable circuit • Removed EEPROM information due to publication of separate guides Published revised design guide information: • Added 82547GI coverage • Removed Confidential status • Updated schematics, removed redundant caps • Revised LAN disable circuit Added crystal start-up information. Information includes: • New crystal parameters • Crystal selection guidelines • Crystal validation methods • Crystal testing methods Changed signal name FL_SO to the correct signal name FLSH_SO. Added 82562EX applicability. Added new values for TX and RX terminations (next to LAN silicon). New values are now 110 Ω for both TX and RX terminations. Added new starting values for RBIAS100 and RBIAS10. New starting Read the full 82562EZ(EX)/82547GI(EI) Dual Footprint.