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82562ET 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon

Product Features Datasheet ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface ■ IEEE 802.3u Auto-Negotiation support ■ Digital Adaptive Equalization control ■ Link status interrupt capability ■ XOR tree mode support ■ 3-port LED support (speed, link and activity) ■ 10BASE-T auto-polarity correction ■ LAN Connect Interface ■ Diagnostic loopback mode ■ 1:1 transmit transformer ratio support ■ Low power (less than 300 mW in active transmit mode) ■ Reduced power in “unplugged mode” (less than 50 mW) ■ Automatic detection of “unplugged mode” ■ 3.3 V device ■ 48-pin Shrink Small Outline Package Revision 1.4 November 2006 Revision History Revision 0.55 0.6 1.0 1.1 1.2 1.3 1.4 Revision Date Sept. 1999 Nov. 1999 May 2000 June 2000 Oct 2001 March 2003 Nov 2006 Description Initial release. • Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect correct signal transitions. • Removed “10BASE-T Error Detection and Reporting” section since the 82562 does not do 10BASE-T error reporting. • Updated bit 13 of Table 3 “Register 16 (10 Hexadecimal): PLC Status, Con- trol and Address Data” to reflect correct values. Advance Information Datasheet release (Intel Secret). • Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR Tree and include column for comments. • Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”. • Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to Table 1 “82562ET Hardware Configuration”. • Updated Section 6.0, “Electrical and Timing Specifications”. • Replaced diagrams in Section 7.1, “Package Information”. Advance Information Datasheet release (Intel Confidential). • On cover page, replaced Boundary Scan Support with XOR tree mode support. Added bullet for LAN Connect I/F. • Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but replaced EM with ET in diagram. • Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”. • Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0. Removed confidential status. • Removed sections: “Physical Layer Interface Functionality” and “Platform LAN Connect”. • Changed “Electrical and Timing Specifications” section to “Voltage and Temperature Specifications” and removed timing specifications. • Added product ordering code in Section 1.0. • Corrected the TESTEN signal description. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked Read the full 82562ET 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon.

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